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Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.h')
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 06a51ae5eb..2d4ec1d3d7 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -18,6 +18,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "PPC.h"
+#include "PPCSubtarget.h"
namespace llvm {
namespace PPCISD {
@@ -168,8 +169,9 @@ namespace llvm {
class PPCTargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.
+ const PPCSubtarget &PPCSubTarget;
public:
- PPCTargetLowering(TargetMachine &TM);
+ PPCTargetLowering(PPCTargetMachine &TM);
/// getTargetNodeName() - This method returns the name of a target specific
/// DAG node.
@@ -191,9 +193,9 @@ namespace llvm {
MachineBasicBlock *MBB);
ConstraintType getConstraintType(char ConstraintLetter) const;
- std::vector<unsigned>
- getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const;
+ std::pair<unsigned, const TargetRegisterClass*>
+ getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const;
SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
SelectionDAG &DAG);