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Diffstat (limited to 'lib/Target/PowerPC/PPC64ISelPattern.cpp')
-rw-r--r--lib/Target/PowerPC/PPC64ISelPattern.cpp190
1 files changed, 95 insertions, 95 deletions
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 5604a9e8e5..e196a2bec6 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -4,7 +4,7 @@
//
// This file was developed by Nate Begeman and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for 64 bit PowerPC.
@@ -45,7 +45,7 @@ namespace {
addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC64::FPRCRegisterClass);
-
+
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
@@ -62,7 +62,7 @@ namespace {
setShiftAmountFlavor(Extend); // shl X, 32 == 0
addLegalFPImmediate(+0.0); // Necessary for FSEL
- addLegalFPImmediate(-0.0); //
+ addLegalFPImmediate(-0.0); //
computeRegisterProperties();
}
@@ -71,16 +71,16 @@ namespace {
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
-
+
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand, SDOperand>
LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand,SDOperand>
LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
const Type *ArgTy, SelectionDAG &DAG);
@@ -101,8 +101,8 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock& BB = MF.front();
std::vector<SDOperand> ArgValues;
-
- // Due to the rather complicated nature of the PowerPC ABI, rather than a
+
+ // Due to the rather complicated nature of the PowerPC ABI, rather than a
// fixed size array of physical args, for the sake of simplicity let the STL
// handle tracking them for us.
std::vector<unsigned> argVR, argPR, argOp;
@@ -110,7 +110,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
@@ -126,13 +126,13 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SDOperand newroot, argt;
bool needsLoad = false;
MVT::ValueType ObjectVT = getValueType(I->getType());
-
+
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
- case MVT::i32:
+ case MVT::i32:
case MVT::i64:
if (GPR_remaining > 0) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
@@ -148,7 +148,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
case MVT::f64:
if (FPR_remaining > 0) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
- argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
+ argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
DAG.getRoot());
--FPR_remaining;
++FPR_idx;
@@ -157,9 +157,9 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
}
break;
}
-
+
// We need to load the argument to a virtual register if we determined above
- // that we ran out of physical registers of the appropriate type
+ // that we ran out of physical registers of the appropriate type
if (needsLoad) {
unsigned SubregOffset = 0;
switch (ObjectVT) {
@@ -167,18 +167,18 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
case MVT::i1:
case MVT::i8: SubregOffset = 7; break;
case MVT::i16: SubregOffset = 6; break;
- case MVT::i32:
+ case MVT::i32:
case MVT::f32: SubregOffset = 4; break;
- case MVT::i64:
+ case MVT::i64:
case MVT::f64: SubregOffset = 0; break;
}
int FI = MFI->CreateFixedObject(8, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
+ FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
DAG.getConstant(SubregOffset, MVT::i64));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
}
-
+
// Every 4 bytes of argument space consumes one of the GPRs available for
// argument passing.
if (GPR_remaining > 0) {
@@ -186,7 +186,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
++GPR_idx;
}
ArgOffset += 8;
-
+
DAG.setRoot(newroot.getValue(1));
ArgValues.push_back(argt);
}
@@ -203,7 +203,7 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i64, DAG.getRoot());
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+ SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
Val, FIN);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
@@ -233,8 +233,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
DAG.getConstant(NumBytes, getPointerTy()));
} else {
NumBytes = 8 * Args.size(); // All arguments are rounded up to 8 bytes
-
- // Just to be safe, we'll always reserve the full 48 bytes of linkage area
+
+ // Just to be safe, we'll always reserve the full 48 bytes of linkage area
// plus 64 bytes of argument space in case any called code gets funky on us.
if (NumBytes < 112) NumBytes = 112;
@@ -248,7 +248,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
// passing.
SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
DAG.getEntryNode());
-
+
// Figure out which arguments are going to go in registers, and which in
// memory. Also, if this is a vararg function, floating point operations
// must be stored to our stack, and loaded into integer regs as well, if
@@ -256,7 +256,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
unsigned ArgOffset = 48;
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
-
+
std::vector<SDOperand> MemOps;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
// PtrOff will be used to store the current argument to the stack if a
@@ -264,7 +264,7 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
MVT::ValueType ArgVT = getValueType(Args[i].second);
-
+
switch (ArgVT) {
default: assert(0 && "Unexpected ValueType for argument!");
case MVT::i1:
@@ -323,14 +323,14 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
}
-
+
std::vector<MVT::ValueType> RetVals;
MVT::ValueType RetTyVT = getValueType(RetTy);
if (RetTyVT != MVT::isVoid)
RetVals.push_back(RetTyVT);
RetVals.push_back(MVT::Other);
- SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
+ SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
Chain, Callee, args_to_use), 0);
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
@@ -357,7 +357,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
}
return std::make_pair(Result, Chain);
}
-
+
std::pair<SDOperand, SDOperand> PPC64TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
@@ -374,10 +374,10 @@ Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
/// SelectionDAG operations.
//===--------------------------------------------------------------------===//
class ISel : public SelectionDAGISel {
-
+
/// Comment Here.
PPC64TargetLowering PPC64Lowering;
-
+
/// ExprMap - As shared expressions are codegen'd, we keep track of which
/// vreg the value is produced in, so we only emit one copy of each compiled
/// tree.
@@ -385,37 +385,37 @@ class ISel : public SelectionDAGISel {
unsigned GlobalBaseReg;
bool GlobalBaseInitialized;
-
+
public:
- ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
+ ISel(TargetMachine &TM) : SelectionDAGISel(PPC64Lowering), PPC64Lowering(TM)
{}
-
+
/// runOnFunction - Override this function in order to reset our per-function
/// variables.
virtual bool runOnFunction(Function &Fn) {
// Make sure we re-emit a set of the global base reg if necessary
GlobalBaseInitialized = false;
return SelectionDAGISel::runOnFunction(Fn);
- }
-
+ }
+
/// InstructionSelectBasicBlock - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
DEBUG(BB->dump());
// Codegen the basic block.
Select(DAG.getRoot());
-
+
// Clear state used for selection.
ExprMap.clear();
}
-
+
unsigned getGlobalBaseReg();
unsigned getConstDouble(double floatVal, unsigned Result);
unsigned SelectSetCR0(SDOperand CC);
unsigned SelectExpr(SDOperand N);
unsigned SelectExprFP(SDOperand N, unsigned Result);
void Select(SDOperand N);
-
+
bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
void SelectBranchCC(SDOperand N);
};
@@ -435,7 +435,7 @@ static unsigned ExactLog2(unsigned Val) {
/// getImmediateForOpcode - This method returns a value indicating whether
/// the ConstantSDNode N can be used as an immediate to Opcode. The return
/// values are either 0, 1 or 2. 0 indicates that either N is not a
-/// ConstantSDNode, or is not suitable for use by that opcode. A return value
+/// ConstantSDNode, or is not suitable for use by that opcode. A return value
/// of 1 indicates that the constant may be used in normal immediate form. A
/// return value of 2 indicates that the constant may be used in shifted
/// immediate form. A return value of 3 indicates that log base 2 of the
@@ -446,7 +446,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
if (N.getOpcode() != ISD::Constant) return 0;
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-
+
switch(Opcode) {
default: return 0;
case ISD::ADD:
@@ -528,7 +528,7 @@ unsigned ISel::getGlobalBaseReg() {
return GlobalBaseReg;
}
-/// getConstDouble - Loads a floating point value into a register, via the
+/// getConstDouble - Loads a floating point value into a register, via the
/// Constant Pool. Optionally takes a register in which to load the value.
unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
unsigned Tmp1 = MakeReg(MVT::i64);
@@ -544,9 +544,9 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
unsigned ISel::SelectSetCR0(SDOperand CC) {
unsigned Opc, Tmp1, Tmp2;
- static const unsigned CompareOpcodes[] =
+ static const unsigned CompareOpcodes[] =
{ PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-
+
// If the first operand to the select is a SETCC node, then we can fold it
// into the branch that selects which value to return.
SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
@@ -557,7 +557,7 @@ unsigned ISel::SelectSetCR0(SDOperand CC) {
// Pass the optional argument U to getImmediateForOpcode for SETCC,
// so that it knows whether the SETCC immediate range is signed or not.
- if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
+ if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
Tmp2, U)) {
if (U)
BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
@@ -586,7 +586,7 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
offset = imm;
return false;
- }
+ }
offset = SelectExpr(N.getOperand(1));
return true;
}
@@ -598,14 +598,14 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
void ISel::SelectBranchCC(SDOperand N)
{
assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
- MachineBasicBlock *Dest =
+ MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
// Get the MBB we will fall through to so that we can hand it off to the
// branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
//ilist<MachineBasicBlock>::iterator It = BB;
//MachineBasicBlock *Fallthrough = ++It;
-
+
Select(N.getOperand(0)); //chain
unsigned Opc = SelectSetCR0(N.getOperand(1));
// FIXME: Use this once we have something approximating two-way branches
@@ -645,7 +645,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-
+
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
switch(SetCC->getCondition()) {
@@ -704,12 +704,12 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
assert(0 && "Should never get here");
return 0;
}
-
+
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
Opc = SelectSetCR0(N.getOperand(0));
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -749,7 +749,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
}
case ISD::FNEG:
- if (!NoExcessFPPrecision &&
+ if (!NoExcessFPPrecision &&
ISD::ADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -760,7 +760,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- } else if (!NoExcessFPPrecision &&
+ } else if (!NoExcessFPPrecision &&
ISD::SUB == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -779,23 +779,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
}
return Result;
-
+
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
- assert (DestType == MVT::f32 &&
- N.getOperand(0).getValueType() == MVT::f64 &&
+ assert (DestType == MVT::f32 &&
+ N.getOperand(0).getValueType() == MVT::f64 &&
"only f64 to f32 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_EXTEND:
- assert (DestType == MVT::f64 &&
- N.getOperand(0).getValueType() == MVT::f32 &&
+ assert (DestType == MVT::f64 &&
+ N.getOperand(0).getValueType() == MVT::f32 &&
"only f32 to f64 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
@@ -807,13 +807,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
return Result;
-
+
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
Result = getConstDouble(CN->getValue(), Result);
return Result;
}
-
+
case ISD::ADD:
if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
N.getOperand(0).Val->hasOneUse()) {
@@ -866,10 +866,10 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
Tmp3 = MakeReg(MVT::i64); // temp reg to hold the conversion constant
unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
-
+
int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
MachineConstantPool *CP = BB->getParent()->getConstantPool();
-
+
// FIXME: pull this FP constant generation stuff out into something like
// the simple ISel's getReg.
if (IsUnsigned) {
@@ -935,7 +935,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (ISD::CopyFromReg == opcode)
DestType = N.getValue(0).getValueType();
-
+
if (DestType == MVT::f64 || DestType == MVT::f32)
if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
return SelectExprFP(N, Result);
@@ -983,7 +983,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
return Result;
-
+
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
Tmp1 = MakeReg(MVT::i64);
@@ -1004,7 +1004,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
bool sext = (ISD::SEXTLOAD == opcode);
-
+
// Make sure we generate both values.
if (Result != 1)
ExprMap[N.getValue(1)] = 1; // Generate the token
@@ -1025,7 +1025,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::f32: Opc = PPC::LFS; break;
case MVT::f64: Opc = PPC::LFD; break;
}
-
+
if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
Tmp1 = MakeReg(MVT::i64);
int CPI = CP->getIndex();
@@ -1048,10 +1048,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
return Result;
}
-
+
case ISD::CALL: {
unsigned GPR_idx = 0, FPR_idx = 0;
- static const unsigned GPR[] = {
+ static const unsigned GPR[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
@@ -1066,13 +1066,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
MachineInstr *CallMI;
// Emit the correct call instruction based on the type of symbol called.
- if (GlobalAddressSDNode *GASD =
+ if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
true);
- } else if (ExternalSymbolSDNode *ESSDN =
+ } else if (ExternalSymbolSDNode *ESSDN =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
- CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
+ CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
true);
} else {
Tmp1 = SelectExpr(N.getOperand(1));
@@ -1081,7 +1081,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
.addReg(PPC::R12);
}
-
+
// Load the register args to virtual regs
std::vector<unsigned> ArgVR;
for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
@@ -1112,7 +1112,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
break;
}
}
-
+
// Put the call instruction in the correct place in the MachineBasicBlock
BB->push_back(CallMI);
@@ -1140,20 +1140,20 @@ unsigned ISel::SelectExpr(SDOperand N) {
switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
case MVT::i32:
- BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);
break;
case MVT::i16:
- BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
break;
case MVT::i8:
- BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
break;
case MVT::i1:
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
break;
}
return Result;
-
+
case ISD::CopyFromReg:
if (Result == 1)
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
@@ -1172,7 +1172,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, PPC::SLD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRL:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1184,7 +1184,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, PPC::SRD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::SRA:
Tmp1 = SelectExpr(N.getOperand(0));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1195,7 +1195,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, PPC::SRAD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
-
+
case ISD::ADD:
Tmp1 = SelectExpr(N.getOperand(0));
switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
@@ -1302,7 +1302,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
}
return Result;
-
+
case ISD::MUL:
Tmp1 = SelectExpr(N.getOperand(0));
if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
@@ -1338,23 +1338,23 @@ unsigned ISel::SelectExpr(SDOperand N) {
addFrameReference(BuildMI(BB, PPC::LD, 2, Result), FrameIdx);
return Result;
}
-
+
case ISD::SETCC:
if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
Opc = SelectSetCR0(N);
-
+
unsigned TrueValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
unsigned FalseValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
ilist<MachineBasicBlock>::iterator It = BB;
++It;
-
+
// thisMBB:
// ...
// cmpTY cr0, r1, r2
@@ -1387,13 +1387,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
assert(0 && "Is this legal?");
return 0;
-
+
case ISD::SELECT: {
unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
Opc = SelectSetCR0(N.getOperand(0));
- // Create an iterator with which to insert the MBB for copying the false
+ // Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1467,7 +1467,7 @@ void ISel::Select(SDOperand N) {
return; // Already selected.
SDNode *Node = N.Val;
-
+
switch (Node->getOpcode()) {
default:
Node->dump(); std::cerr << "\n";
@@ -1492,16 +1492,16 @@ void ISel::Select(SDOperand N) {
BuildMI(BB, PPC::B, 1).addMBB(Dest);
return;
}
- case ISD::BRCOND:
+ case ISD::BRCOND:
SelectBranchCC(N);
return;
case ISD::CopyToReg:
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = cast<RegSDNode>(N)->getReg();
-
+
if (Tmp1 != Tmp2) {
- if (N.getOperand(1).getValueType() == MVT::f64 ||
+ if (N.getOperand(1).getValueType() == MVT::f64 ||
N.getOperand(1).getValueType() == MVT::f32)
BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
else
@@ -1546,8 +1546,8 @@ void ISel::Select(SDOperand N) {
}
BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
return;
- case ISD::TRUNCSTORE:
- case ISD::STORE:
+ case ISD::TRUNCSTORE:
+ case ISD::STORE:
{
SDOperand Chain = N.getOperand(0);
SDOperand Value = N.getOperand(1);
@@ -1582,7 +1582,7 @@ void ISel::Select(SDOperand N) {
{
int offset;
bool idx = SelectAddr(Address, Tmp2, offset);
- if (idx) {
+ if (idx) {
Opc = IndexedOpForOp(Opc);
BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
} else {
@@ -1611,6 +1611,6 @@ void ISel::Select(SDOperand N) {
/// description file.
///
FunctionPass *llvm::createPPC64ISelPattern(TargetMachine &TM) {
- return new ISel(TM);
+ return new ISel(TM);
}
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-27 20:56:17 +0000