diff options
Diffstat (limited to 'lib/Target/CellSPU/SPUInstrInfo.td')
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 2287 |
1 files changed, 1502 insertions, 785 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 7f86ae14d5..cfe47c6d32 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -374,53 +374,45 @@ def ILHUf32: // ILHUhi: Used for loading high portion of an address. Note the symbolHi // printer used for the operand. -def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val), +def ILHUhi: + RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val), "ilhu\t$rT, $val", ImmLoad, [(set R32C:$rT, hi16:$val)]>; // Immediate load address (can also be used to load 18-bit unsigned constants, // see the zext 16->32 pattern) -def ILAr64: - RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val), - "ila\t$rT, $val", LoadNOP, - [(set R64C:$rT, imm18:$val)]>; - -// TODO: ILAv2i64 - -def ILAv2i64: - RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>; - -def ILAv4i32: - RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>; - -def ILAr32: - RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set R32C:$rT, imm18:$val)]>; - -def ILAf32: - RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val), - "ila\t$rT, $val", LoadNOP, - [(set R32FP:$rT, fpimm18:$val)]>; - -def ILAf64: - RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val), - "ila\t$rT, $val", LoadNOP, - [(set R64FP:$rT, fpimm18:$val)]>; - -def ILAlo: - RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val), - "ila\t$rT, $val", ImmLoad, - [(set R32C:$rT, imm18:$val)]>; - -def ILAlsa: - RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val), - "ila\t$rT, $val", ImmLoad, - [/* no pattern */]>; +class ILAInst<dag OOL, dag IOL, list<dag> pattern>: + RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val", + LoadNOP, pattern>; + +multiclass ImmLoadAddress +{ + def v2i64: ILAInst<(outs VECREG:$rT), (ins u18imm:$val), + [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>; + + def v4i32: ILAInst<(outs VECREG:$rT), (ins u18imm:$val), + [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>; + + def r64: ILAInst<(outs R64C:$rT), (ins u18imm_i64:$val), + [(set R64C:$rT, imm18:$val)]>; + + def r32: ILAInst<(outs R32C:$rT), (ins u18imm:$val), + [(set R32C:$rT, imm18:$val)]>; + + def f32: ILAInst<(outs R32FP:$rT), (ins f18imm:$val), + [(set R32FP:$rT, fpimm18:$val)]>; + + def f64: ILAInst<(outs R64FP:$rT), (ins f18imm_f64:$val), + [(set R64FP:$rT, fpimm18:$val)]>; + + def lo: ILAInst<(outs R32C:$rT), (ins symbolLo:$val), + [(set R32C:$rT, imm18:$val)]>; + + def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val), + [/* no pattern */]>; +} + +defm ILA : ImmLoadAddress; // Immediate OR, Halfword Lower: The "other" part of loading large constants // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...> @@ -465,7 +457,7 @@ class FSMBIVec<ValueType vectype> [(set (vectype VECREG:$rT), (SPUfsmbi immU16:$val))]> { } -multiclass FSMBIs +multiclass FormSelectMaskBytesImm { def v16i8: FSMBIVec<v16i8>; def v8i16: FSMBIVec<v8i16>; @@ -473,7 +465,27 @@ multiclass FSMBIs def v2i64: FSMBIVec<v2i64>; } -defm FSMBI : FSMBIs; +defm FSMBI : FormSelectMaskBytesImm; + +// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits +def FSMB: + RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA), + "fsmb\t$rT, $rA", SelectOp, + []>; + +// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is +// only 8-bits wide (even though it's input as 16-bits here) +def FSMH: + RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA), + "fsmh\t$rT, $rA", SelectOp, + []>; + +// fsm: Form select mask for words. Like the other fsm* instructions, +// only the lower 4 bits of $rA are significant. +def FSM: + RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA), + "fsm\t$rT, $rA", SelectOp, + []>; //===----------------------------------------------------------------------===// // Integer and Logical Operations: @@ -487,8 +499,6 @@ def AHv8i16: def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)), (AHv8i16 VECREG:$rA, VECREG:$rB)>; -// [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; - def AHr16: RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), "ah\t$rT, $rA, $rB", IntegerOp, @@ -500,20 +510,23 @@ def AHIvec: [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; -def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "ahi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>; +def AHIr16: + RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), + "ahi\t$rT, $rA, $val", IntegerOp, + [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>; -def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "a\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; +def Avec: + RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + "a\t$rT, $rA, $rB", IntegerOp, + [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)), (Avec VECREG:$rA, VECREG:$rB)>; -def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "a\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>; +def Ar32: + RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + "a\t$rT, $rA, $rB", IntegerOp, + [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>; def Ar8: RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), @@ -802,26 +815,6 @@ def CNTBv4i32 : "cntb\t$rT, $rA", IntegerOp, [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>; -// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits -def FSMB: - RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsmb\t$rT, $rA", SelectOp, - []>; - -// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is -// only 8-bits wide (even though it's input as 16-bits here) -def FSMH: - RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsmh\t$rT, $rA", SelectOp, - []>; - -// fsm: Form select mask for words. Like the other fsm* instructions, -// only the lower 4 bits of $rA are significant. -def FSM: - RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsm\t$rT, $rA", SelectOp, - []>; - // gbb: Gather all low order bits from each byte in $rA into a single 16-bit // quantity stored into $rT def GBB: @@ -923,281 +916,257 @@ def : Pat<(sext R32C:$inp), (XSWDr32 R32C:$inp)>; // AND operations -def ANDv16i8: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB)))]>; - -def ANDv8i16: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)))]>; -def ANDv4i32: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB)))]>; - -def ANDr32: - RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>; - -//===--------------------------------------------- -// Special instructions to perform the fabs instruction -def ANDfabs32: - RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -def ANDfabs64: - RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -// Could use ANDv4i32, but won't for clarity -def ANDfabsvec: - RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern */]>; - -//===--------------------------------------------- - -def ANDr16: - RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>; - -def ANDr8: - RRForm<0b10000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>; - -// Hacked form of AND to zero-extend 16-bit quantities to 32-bit -// quantities -- see 16->32 zext pattern. -// -// This pattern is somewhat artificial, since it might match some -// compiler generated pattern but it is unlikely to do so. -def AND2To4: - RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB), - "and\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>; +class ANDInst<dag OOL, dag IOL, list<dag> pattern> : + RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ANDVecInst<ValueType vectype>: + ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; + +multiclass BitwiseAnd +{ + def v16i8: ANDVecInst<v16i8>; + def v8i16: ANDVecInst<v8i16>; + def v4i32: ANDVecInst<v4i32>; + def v2i64: ANDVecInst<v2i64>; + + def r64: ANDInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB), + [(set R64C:$rT, (and R64C:$rA, R64C:$rB))]>; + + def r32: ANDInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), + [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>; + + def r16: ANDInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), + [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>; + + def r8: ANDInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), + [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>; + + //===--------------------------------------------- + // Special instructions to perform the fabs instruction + def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), + [/* Intentionally does not match a pattern */]>; + + def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), + [/* Intentionally does not match a pattern */]>; + + // Could use v4i32, but won't for clarity + def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* Intentionally does not match a pattern */]>; + + //===--------------------------------------------- + + // Hacked form of AND to zero-extend 16-bit quantities to 32-bit + // quantities -- see 16->32 zext pattern. + // + // This pattern is somewhat artificial, since it might match some + // compiler generated pattern but it is unlikely to do so. + + def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB), + [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>; +} + +defm AND : BitwiseAnd; // N.B.: vnot_conv is one of those special target selection pattern fragments, // in which we expect there to be a bit_convert on the constant. Bear in mind // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a // constant -1 vector.) -def ANDCv16i8: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA), - (vnot (v16i8 VECREG:$rB))))]>; - -def ANDCv8i16: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA), - (vnot (v8i16 VECREG:$rB))))]>; - -def ANDCv4i32: - RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA), - (vnot (v4i32 VECREG:$rB))))]>; - -def ANDCr32: - RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>; - -def ANDCr16: - RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>; - -def ANDCr8: - RRForm<0b10000011010, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "andc\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, (not R8C:$rB)))]>; - -def ANDBIv16i8: - RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "andbi\t$rT, $rA, $val", IntegerOp, - [(set (v16i8 VECREG:$rT), - (and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>; -def ANDBIr8: - RI10Form<0b01101000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), - "andbi\t$rT, $rA, $val", IntegerOp, - [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>; +class ANDCInst<dag OOL, dag IOL, list<dag> pattern>: + RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB", + IntegerOp, pattern>; -def ANDHIv8i16: - RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set (v8i16 VECREG:$rT), - (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; +class ANDCVecInst<ValueType vectype>: + ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA), + (vnot (vectype VECREG:$rB))))]>; -def ANDHIr16: - RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>; +class ANDCRegInst<RegisterClass rclass>: + ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>; -def ANDHI1To2: - RI10Form<0b10101000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val), - "andhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (and (zext R8C:$rA), i16ImmSExt10:$val))]>; +multiclass AndComplement +{ + def v16i8: ANDCVecInst<v16i8>; + def v8i16: ANDCVecInst<v8i16>; + def v4i32: ANDCVecInst<v4i32>; + def v2i64: ANDCVecInst<v2i64>; + + def r128: ANDCRegInst<GPRC>; + def r64: ANDCRegInst<R64C>; + def r32: ANDCRegInst<R32C>; + def r16: ANDCRegInst<R16C>; + def r8: ANDCRegInst<R8C>; +} -def ANDIv4i32: - RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set (v4i32 VECREG:$rT), - (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>; - -def ANDIr32: - RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>; - -// Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32 -// pattern below. -def ANDI1To4: - RI10Form<0b10101000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and (zext R8C:$rA), i32ImmSExt10:$val))]>; - -// Hacked form of ANDI to zero-extend i16 quantities to i32. See the -// zext 16->32 pattern below. -// -// Note that this pattern is somewhat artificial, since it might match -// something the compiler generates but is unlikely to occur in practice. -def ANDI2To4: - RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), - "andi\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>; +defm ANDC : AndComplement; + +class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>: + RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val", + IntegerOp, pattern>; + +multiclass AndByteImm +{ + def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (v16i8 VECREG:$rT), + (and (v16i8 VECREG:$rA), + (v16i8 v16i8U8Imm:$val)))]>; + + def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), + [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>; +} + +defm ANDBI : AndByteImm; +class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> : + RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val", + IntegerOp, pattern>; + +multiclass AndHalfwordImm +{ + def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v8i16 VECREG:$rT), + (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>; + + def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val), + [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>; + + // Zero-extend i8 to i16: + def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val), + [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>; +} + +defm ANDHI : AndHalfwordImm; + +class ANDIInst<dag OOL, dag IOL, list<dag> pattern> : + RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val", + IntegerOp, pattern>; + +multiclass AndWordImm +{ + def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), + [(set (v4i32 VECREG:$rT), + (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>; + + def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>; + + // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32 + // pattern below. + def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), + [(set R32C:$rT, + (and (zext R8C:$rA), i32ImmSExt10:$val))]>; + + // Hacked form of ANDI to zero-extend i16 quantities to i32. See the + // zext 16->32 pattern below. + // + // Note that this pattern is somewhat artificial, since it might match + // something the compiler generates but is unlikely to occur in practice. + def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), + [(set R32C:$rT, + (and (zext R16C:$rA), i32ImmSExt10:$val))]>; +} + +defm ANDI : AndWordImm; + +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // Bitwise OR group: +//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + // Bitwise "or" (N.B.: These are also register-register copy instructions...) -def ORv16i8: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; - -def ORv8i16: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; - -def ORv4i32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; - -def ORv4f32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v4f32 VECREG:$rT), - (v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>; +class ORInst<dag OOL, dag IOL, list<dag> pattern>: + RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB", + IntegerOp, pattern>; -def ORv2f64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set (v2f64 VECREG:$rT), - (v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>; - -def ORgprc: - RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>; - -def ORr64: - RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>; - -def ORr32: - RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>; - -def ORr16: - RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>; - -def ORr8: - RRForm<0b10000010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>; - -// OR instruction forms that are used to copy f32 and f64 registers. -// They do not match patterns. -def ORf32: - RRForm<0b10000010000, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +class ORVecInst<ValueType vectype>: + ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; -def ORf64: - RRForm<0b10000010000, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +class ORRegInst<RegisterClass rclass>: + ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>; -// ORv*_*: Used in scalar->vector promotions: -def ORv16i8_i8: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; +class ORPromoteScalar<RegisterClass rclass>: + ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB), + [/* no pattern */]>; + +class ORExtractElt<RegisterClass rclass>: + ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern */]>; +multiclass BitwiseOr +{ + def v16i8: ORVecInst<v16i8>; + def v8i16: ORVecInst<v8i16>; + def v4i32: ORVecInst<v4i32>; + def v2i64: ORVecInst<v2i64>; + + def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v4f32 VECREG:$rT), + (v4f32 (bitconvert (or (v4i32 VECREG:$rA), + (v4i32 VECREG:$rB)))))]>; + + def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (v2f64 VECREG:$rT), + (v2f64 (bitconvert (or (v2i64 VECREG:$rA), + (v2i64 VECREG:$rB)))))]>; + + def r64: ORRegInst<R64C>; + def r32: ORRegInst<R32C>; + def r16: ORRegInst<R16C>; + def r8: ORRegInst<R8C>; + + // OR instructions used to copy f32 and f64 registers. + def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB), + [/* no pattern */]>; + + def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB), + [/* no pattern */]>; + + // scalar->vector promotion: + def v16i8_i8: ORPromoteScalar<R8C>; + def v8i16_i16: ORPromoteScalar<R16C>; + def v4i32_i32: ORPromoteScalar<R32C>; + def v2i64_i64: ORPromoteScalar<R64C>; + def v4f32_f32: ORPromoteScalar<R32FP>; + def v2f64_f64: ORPromoteScalar<R64FP>; + + // extract element 0: + def i8_v16i8: ORExtractElt<R8C>; + def i16_v8i16: ORExtractElt<R16C>; + def i32_v4i32: ORExtractElt<R32C>; + def i64_v2i64: ORExtractElt<R64C>; + def f32_v4f32: ORExtractElt<R32FP>; + def f64_v2f64: ORExtractElt<R64FP>; +} + +defm OR : BitwiseOr; + +// scalar->vector promotion patterns: def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)), (ORv16i8_i8 R8C:$rA, R8C:$rA)>; -def ORv8i16_i16: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)), (ORv8i16_i16 R16C:$rA, R16C:$rA)>; -def ORv4i32_i32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)), (ORv4i32_i32 R32C:$rA, R32C:$rA)>; -def ORv2i64_i64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)), (ORv2i64_i64 R64C:$rA, R64C:$rA)>; -def ORv4f32_f32: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)), (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>; -def ORv2f64_f64: - RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)), (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>; // ORi*_v*: Used to extract vector element 0 (the preferred slot) -def ORi8_v16i8: - RRForm<0b10000010000, (outs R8C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)), (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>; @@ -1205,157 +1174,144 @@ def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)), def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)), (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>; -def ORi16_v8i16: - RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)), (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>; def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)), (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>; -def ORi32_v4i32: - RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)), (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>; def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)), (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>; -def ORi64_v2i64: - RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)), (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>; def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)), (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>; -def ORf32_v4f32: - RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)), (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>; def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)), (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>; -def ORf64_v2f64: - RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB), - "or\t$rT, $rA, $rB", IntegerOp, - [/* no pattern */]>; - def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)), (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>; def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)), (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>; -// ORC: Bitwise "or" with complement (match before ORvec, ORr32) -def ORCv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), - (vnot (v16i8 VECREG:$rB))))]>; +// ORC: Bitwise "or" with complement (c = a | ~b) -def ORCv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), - (vnot (v8i16 VECREG:$rB))))]>; +class ORCInst<dag OOL, dag IOL, list<dag> pattern>: + RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB", + IntegerOp, pattern>; -def ORCv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), - (vnot (v4i32 VECREG:$rB))))]>; +class ORCVecInst<ValueType vectype>: + ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + (vnot (vectype VECREG:$rB))))]>; -def ORCr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>; +class ORCRegInst<RegisterClass rclass>: + ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>; -def ORCr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>; +multiclass BitwiseOrComplement +{ + def v16i8: ORCVecInst<v16i8>; + def v8i16: ORCVecInst<v8i16>; + def v4i32: ORCVecInst<v4i32>; + def v2i64: ORCVecInst<v2i64>; + + def r64: ORCRegInst<R64C>; + def r32: ORCRegInst<R32C>; + def r16: ORCRegInst<R16C>; + def r8: ORCRegInst<R8C>; +} -def ORCr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "orc\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, (not R8C:$rB)))]>; +defm ORC : BitwiseOrComplement; // OR byte immediate -def ORBIv16i8: - RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "orbi\t$rT, $rA, $val", IntegerOp, - [(set (v16i8 VECREG:$rT), - (or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>; +class ORBIInst<dag OOL, dag IOL, list<dag> pattern>: + RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val", + IntegerOp, pattern>; + +class ORBIVecInst<ValueType vectype, PatLeaf immpred>: + ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA), + (vectype immpred:$val)))]>; -def ORBIr8: - RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), - "orbi\t$rT, $rA, $val", IntegerOp, - [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>; +multiclass BitwiseOrByteImm +{ + def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>; + + def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val), + [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>; +} + +defm ORBI : BitwiseOrByteImm; // OR halfword immediate -def ORHIv8i16: - RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), - v8i16Uns10Imm:$val))]>; +class ORHIInst<dag OOL, dag IOL, list<dag> pattern>: + RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val", + IntegerOp, pattern>; -def ORHIr16: - RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, u10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>; +class ORHIVecInst<ValueType vectype, PatLeaf immpred>: + ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + immpred:$val))]>; + +multiclass BitwiseOrHalfwordImm +{ + def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>; + + def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val), + [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>; + + // Specialized ORHI form used to promote 8-bit registers to 16-bit + def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val), + [(set R16C:$rT, (or (anyext R8C:$rA), + i16ImmSExt10:$val))]>; +} -// Hacked form of ORHI used to promote 8-bit registers to 16-bit -def ORHI1To2: - RI10Form<0b10100000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val), - "orhi\t$rT, $rA, $val", IntegerOp, - [(set R16C:$rT, (or (anyext R8C:$rA), i16ImmSExt10:$val))]>; +defm ORHI : BitwiseOrHalfwordImm; + +class ORIInst<dag OOL, dag IOL, list<dag> pattern>: + RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val", + IntegerOp, pattern>; + +class ORIVecInst<ValueType vectype, PatLeaf immpred>: + ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), + [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA), + immpred:$val))]>; // Bitwise "or" with immediate -def ORIv4i32: - RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), - v4i32Uns10Imm:$val))]>; - -def ORIr32: - RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>; - -def ORIr64: - RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [/* no pattern */]>; +multiclass BitwiseOrImm +{ + def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>; + + def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val), + [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>; + + // i16i32: hacked version of the ori instruction to extend 16-bit quantities + // to 32-bit quantities. used exclusively to match "anyext" conversions (vide + // infra "anyext 16->32" pattern.) + def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (or (anyext R16C:$rA), + i32ImmSExt10:$val))]>; + + // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities + // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide + // infra "anyext 16->32" pattern.) + def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val), + [(set R32C:$rT, (or (anyext R8C:$rA), + i32ImmSExt10:$val))]>; +} -// ORI2To4: hacked version of the ori instruction to extend 16-bit quantities -// to 32-bit quantities. used exclusively to match "anyext" conversions (vide -// infra "anyext 16->32" pattern.) -def ORI2To4: - RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val), - "ori\t$rT, $rA, $val", IntegerOp, - [(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>; - -// ORI1To4: Hacked version of the ORI instruction to extend 16-bit quantities -// to 32-bit quantities. Used exclusively to match "anyext" conversions (vide -// infra "anyext 16->32" pattern.) -def ORI1To4: |