diff options
Diffstat (limited to 'lib/Target/ARM/ARMInstrFormats.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 249 |
1 files changed, 123 insertions, 126 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 2a30e777ee..6de2d577dd 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -47,15 +47,13 @@ class UnaryDP { bit isUnaryDataProc = 1; } // ARM Instruction templates. // -class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, +class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, Format f, string cstr> : Instruction { field bits<32> Inst; let Namespace = "ARM"; - bits<4> Opcode = opcod; - // TSFlagsFields AddrMode AM = am; bits<4> AddrModeBits = AM.Value; @@ -78,7 +76,7 @@ class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, } class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> - : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { + : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; @@ -86,10 +84,10 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> } // Almost all ARM instructions are predicable. -class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, +class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, Format f, string opc, string asm, string cstr, list<dag> pattern> - : InstARM<opcod, am, sz, im, f, cstr> { + : InstARM<am, sz, im, f, cstr> { let OutOperandList = oops; let InOperandList = !con(iops, (ops pred:$p)); let AsmString = !strconcat(opc, !strconcat("${p}", asm)); @@ -100,10 +98,10 @@ class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, // Same as I except it can optionally modify CPSR. Note it's modeled as // an input operand since by default it's a zero register. It will // become an implicit def once it's "flipped". -class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, +class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, Format f, string opc, string asm, string cstr, list<dag> pattern> - : InstARM<opcod, am, sz, im, f, cstr> { + : InstARM<am, sz, im, f, cstr> { let OutOperandList = oops; let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); @@ -112,9 +110,9 @@ class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, } // Special cases -class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, +class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, Format f, string asm, string cstr, list<dag> pattern> - : InstARM<opcod, am, sz, im, f, cstr> { + : InstARM<am, sz, im, f, cstr> { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; @@ -122,46 +120,46 @@ class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, list<Predicate> Predicates = [IsARM]; } -class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, asm,"",pattern>; -class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AsI<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, asm,"",pattern>; -class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, "", pattern>; // Ctrl flow instructions class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, asm,"",pattern> { let Inst{27-24} = opcod; } class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{27-24} = opcod; } // FIXME: BX -class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXIx2<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm, "", pattern>; class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{27-24} = opcod; } class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, asm,"",pattern> { let Inst{27-24} = opcod; } @@ -169,7 +167,7 @@ class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc, // BR_JT instructions // == mov pc class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, + : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, asm, "", pattern> { let Inst{20} = 0; // S Bit let Inst{24-21} = opcod; @@ -177,7 +175,7 @@ class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> } // == add pc class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, + : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, asm, "", pattern> { let Inst{20} = 0; // S bit let Inst{24-21} = opcod; @@ -185,7 +183,7 @@ class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> } // == ldr pc class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, + : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -198,43 +196,43 @@ class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> // addrmode1 instructions class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{24-21} = opcod; let Inst{27-26} = {0,0}; } class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, + : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{24-21} = opcod; let Inst{27-26} = {0,0}; } class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{24-21} = opcod; let Inst{27-26} = {0,0}; } -class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI1x2<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, asm, "", pattern>; // addrmode2 loads and stores -class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{27-26} = {0,1}; } // loads -class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldw<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -242,9 +240,9 @@ class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI2ldw<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -252,9 +250,9 @@ class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldb<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -262,9 +260,9 @@ class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI2ldb<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -274,9 +272,9 @@ class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm, } // stores -class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stw<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -284,9 +282,9 @@ class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI2stw<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -294,9 +292,9 @@ class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stb<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -304,9 +302,9 @@ class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI2stb<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -316,9 +314,9 @@ class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm, } // Pre-indexed loads -class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldwpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit @@ -326,9 +324,9 @@ class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldbpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{20} = 1; // L bit let Inst{21} = 1; // W bit @@ -338,9 +336,9 @@ class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Pre-indexed stores -class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stwpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{20} = 0; // L bit let Inst{21} = 1; // W bit @@ -348,9 +346,9 @@ class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 1; // P bit let Inst{27-26} = {0,1}; } -class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stbpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{20} = 0; // L bit let Inst{21} = 1; // W bit @@ -360,9 +358,9 @@ class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Post-indexed loads -class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldwpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -370,9 +368,9 @@ class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 0; // P bit let Inst{27-26} = {0,1}; } -class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2ldbpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{20} = 1; // L bit let Inst{21} = 0; // W bit @@ -382,9 +380,9 @@ class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Post-indexed stores -class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stwpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -392,9 +390,9 @@ class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{24} = 0; // P bit let Inst{27-26} = {0,1}; } -class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI2stbpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{20} = 0; // L bit let Inst{21} = 0; // W bit @@ -404,19 +402,19 @@ class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // addrmode3 instructions -class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern>; -class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI3<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, "", pattern>; // loads -class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldh<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -426,9 +424,9 @@ class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI3ldh<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -438,9 +436,9 @@ class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldsh<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -450,9 +448,9 @@ class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI3ldsh<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -462,9 +460,9 @@ class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldsb<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 0; // H bit @@ -474,9 +472,9 @@ class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI3ldsb<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 0; // H bit @@ -486,9 +484,9 @@ class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldd<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 0; // H bit @@ -500,9 +498,9 @@ class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // stores -class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3sth<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -512,9 +510,9 @@ class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI3sth<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, + : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -524,9 +522,9 @@ class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm, let Inst{21} = 0; // W bit let Inst{24} = 1; // P bit } -class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3std<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -538,9 +536,9 @@ class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Pre-indexed loads -class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldhpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -550,9 +548,9 @@ class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit } -class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldshpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -562,9 +560,9 @@ class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 1; // W bit let Inst{24} = 1; // P bit } -class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldsbpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{4} = 1; let Inst{5} = 0; // H bit @@ -576,9 +574,9 @@ class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Pre-indexed stores -class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3sthpr<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, asm, cstr, pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -590,9 +588,9 @@ class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Post-indexed loads -class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldhpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -602,9 +600,9 @@ class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit } -class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldshpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -614,9 +612,9 @@ class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, let Inst{21} = 1; // W bit let Inst{24} = 0; // P bit } -class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3ldsbpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{4} = 1; let Inst{5} = 0; // H bit @@ -628,9 +626,9 @@ class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, } // Post-indexed stores -class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI3sthpo<dag oops, dag iops, Format f, string opc, string asm, string cstr, list<dag> pattern> - : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, + : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, asm, cstr,pattern> { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -643,30 +641,30 @@ class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, // addrmode4 instructions -class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc, +class AI4<dag oops, dag iops, Format f, string opc, string asm, list<dag> pattern> - : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc, + : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc, asm, "", pattern> { let Inst{25-27} = {0,0,1}; } -class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{22} = 0; // S bit let Inst{27-25} = 0b100; } -class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI4ldpc<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 1; // L bit let Inst{27-25} = 0b100; } -class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm, +class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> - : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, + : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, "", pattern> { let Inst{20} = 0; // L bit let Inst{22} = 0; // S bit @@ -674,41 +672,41 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm, } // Unsigned multiply, multiply-accumulate instructions. -class AMul1I<bits<7> mulopc, dag oops, dag iops, string opc, +class AMul1I<bits<7> opcod, dag oops, dag iops, string opc, string asm, list<dag> pattern> - : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, asm,"",pattern> { let Inst{7-4} = 0b1001; let Inst{20} = 0; // S bit - let Inst{27-21} = mulopc; + let Inst{27-21} = opcod; } -class AsMul1I<bits<7> mulopc, dag oops, dag iops, string opc, +class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, string asm, list<dag> pattern> - : sI<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, + : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, asm,"",pattern> { let Inst{7-4} = 0b1001; - let Inst{27-21} = mulopc; + let Inst{27-21} = opcod; } // Most significant word multiply -class AMul2I<bits<7> mulopc, dag oops, dag iops, string opc, +class AMul2I<bits<7> opcod, dag oops, dag iops, string opc, string asm, list<dag> pattern> - : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, asm,"",pattern> { let Inst{7-4} = 0b1001; let Inst{20} = 1; - let Inst{27-21} = mulopc; + let Inst{27-21} = opcod; } // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> -class AMulxyI<bits<7> mulopc, dag oops, dag iops, string opc, +class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, string asm, list<dag> pattern> - : I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, asm,"",pattern> { let Inst{4} = 0; let Inst{7} = 1; let Inst{20} = 0; - let Inst{27-21} = mulopc; + let Inst{27-21} = opcod; } //===----------------------------------------------------------------------===// @@ -734,8 +732,7 @@ class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, string asm, string cstr, list<dag> pattern> - // FIXME: Set all opcodes to 0 for now. - : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> { + : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { let OutOperandList = outs; let InOperandList = ins; let AsmString = asm; |