diff options
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/PrologEpilogInserter.cpp | 9 | ||||
| -rw-r--r-- | lib/CodeGen/RegAllocLocal.cpp | 4 | ||||
| -rw-r--r-- | lib/CodeGen/RegAllocSimple.cpp | 4 | ||||
| -rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 12 |
4 files changed, 11 insertions, 18 deletions
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 1a07013ac3..d9443c83e7 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -206,10 +206,8 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) { MachineBasicBlock *MBB = Fn.begin(); MachineBasicBlock::iterator I = MBB->begin(); for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) { - const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]); - - // Insert the spill to the stack frame... - RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i], RC); + // Insert the spill to the stack frame. + RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]); } // Add code to restore the callee-save registers in each exiting block. @@ -221,8 +219,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) { I = MBB->end(); --I; for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) { - const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]); - RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i], RC); + RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i],StackSlots[i]); --I; // Insert in reverse order } } diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index bea603ce49..68d5fd95ee 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -267,7 +267,7 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DEBUG(std::cerr << " to stack slot #" << FrameIndex); - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex); ++NumStores; // Update statistics } @@ -506,7 +506,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, << RegInfo->getName(PhysReg) << "\n"); // Add move instruction(s) - RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); + RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex); ++NumLoads; // Update statistics MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 4c1e371c72..320b267933 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -131,7 +131,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, // Add move instruction(s) ++NumLoads; - RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx); return PhysReg; } @@ -143,7 +143,7 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, // Add move instruction(s) ++NumStores; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx); } diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 572bace594..e84652ece0 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -144,8 +144,7 @@ namespace { *mbbi, mii, physReg, - vrm.getStackSlot(virtReg), - mf.getSSARegMap()->getRegClass(virtReg)); + vrm.getStackSlot(virtReg)); loaded[virtReg] = true; DEBUG(std::cerr << '\t'; prior(mii)->print(std::cerr, &tm)); @@ -157,8 +156,7 @@ namespace { *mbbi, next(mii), physReg, - vrm.getStackSlot(virtReg), - mf.getSSARegMap()->getRegClass(virtReg)); + vrm.getStackSlot(virtReg)); ++numStores; } mii->SetMachineOperandReg(i, physReg); @@ -226,8 +224,7 @@ namespace { mri_->storeRegToStackSlot(*lastDef->getParent(), nextLastRef, physReg, - vrm_->getStackSlot(virtReg), - mri_->getRegClass(physReg)); + vrm_->getStackSlot(virtReg)); ++numStores; DEBUG(std::cerr << "added: "; prior(nextLastRef)->print(std::cerr, tm_); @@ -258,8 +255,7 @@ namespace { // load if necessary if (vrm_->hasStackSlot(virtReg)) { mri_->loadRegFromStackSlot(mbb, mii, physReg, - vrm_->getStackSlot(virtReg), - mri_->getRegClass(physReg)); + vrm_->getStackSlot(virtReg)); ++numLoads; DEBUG(std::cerr << "added: "; prior(mii)->print(std::cerr, tm_)); |