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-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp24
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp10
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp2
5 files changed, 23 insertions, 23 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index eb6481c996..0527275565 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5444,7 +5444,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
// fold select C, 16, 0 -> shl C, 4
if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
- TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
+ TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
// If the caller doesn't want us to simplify this into a zext of a compare,
// don't do it.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 179329b590..6e781076b8 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -698,19 +698,19 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
// Make sure the extra bits coming from type promotion conform to
- // getSetCCResultContents.
+ // getBooleanContents.
unsigned CondBits = Cond.getValueSizeInBits();
- switch (TLI.getSetCCResultContents()) {
+ switch (TLI.getBooleanContents()) {
default:
- assert(false && "Unknown SetCCResultValue!");
- case TargetLowering::UndefinedSetCCResult:
+ assert(false && "Unknown BooleanContent!");
+ case TargetLowering::UndefinedBooleanContent:
// The promoted value, which may contain rubbish in the upper bits, is fine.
break;
- case TargetLowering::ZeroOrOneSetCCResult:
+ case TargetLowering::ZeroOrOneBooleanContent:
if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
break;
- case TargetLowering::ZeroOrNegativeOneSetCCResult:
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
if (DAG.ComputeNumSignBits(Cond) != CondBits)
Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
DAG.getValueType(MVT::i1));
@@ -830,27 +830,27 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
- // Make sure the extra bits conform to getSetCCResultContents. There are
+ // Make sure the extra bits conform to getBooleanContents. There are
// two sets of extra bits: those in Cond, which come from type promotion,
// and those we need to add to have the final type be SVT (for most targets
// this last set of bits is empty).
unsigned CondBits = Cond.getValueSizeInBits();
ISD::NodeType ExtendCode;
- switch (TLI.getSetCCResultContents()) {
+ switch (TLI.getBooleanContents()) {
default:
- assert(false && "Unknown SetCCResultValue!");
- case TargetLowering::UndefinedSetCCResult:
+ assert(false && "Unknown BooleanContent!");
+ case TargetLowering::UndefinedBooleanContent:
// Extend to SVT by adding rubbish.
ExtendCode = ISD::ANY_EXTEND;
break;
- case TargetLowering::ZeroOrOneSetCCResult:
+ case TargetLowering::ZeroOrOneBooleanContent:
ExtendCode = ISD::ZERO_EXTEND;
if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
// All extra bits need to be cleared. Do this by zero extending the
// original condition value all the way to SVT.
Cond = N->getOperand(0);
break;
- case TargetLowering::ZeroOrNegativeOneSetCCResult: {
+ case TargetLowering::ZeroOrNegativeOneBooleanContent: {
ExtendCode = ISD::SIGN_EXTEND;
unsigned SignBits = DAG.ComputeNumSignBits(Cond);
if (SignBits != CondBits)
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index acd42a05ba..4d60211426 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -210,8 +210,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
if (NVT.bitsLE(SVT)) {
// The SETCC result type is bigger than the vector element type.
// Ensure the SETCC result is sign-extended.
- if (TLI.getSetCCResultContents() !=
- TargetLowering::ZeroOrNegativeOneSetCCResult)
+ if (TLI.getBooleanContents() !=
+ TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
DAG.getValueType(MVT::i1));
// Truncate to the final type.
@@ -219,8 +219,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
} else {
// The SETCC result type is smaller than the vector element type.
// If the SetCC result is not sign-extended, chop it down to MVT::i1.
- if (TLI.getSetCCResultContents() !=
- TargetLowering::ZeroOrNegativeOneSetCCResult)
+ if (TLI.getBooleanContents() !=
+ TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 7d64b2441d..f55bdec968 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1495,10 +1495,10 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
case ISD::UADDO:
if (Op.getResNo() != 1)
return;
- // The boolean result conforms to getSetCCResultContents. Fall through.
+ // The boolean result conforms to getBooleanContents. Fall through.
case ISD::SETCC:
// If we know the result of a setcc has the top bits zero, use this info.
- if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult &&
+ if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
BitWidth > 1)
KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
return;
@@ -1903,11 +1903,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
case ISD::UADDO:
if (Op.getResNo() != 1)
break;
- // The boolean result conforms to getSetCCResultContents. Fall through.
+ // The boolean result conforms to getBooleanContents. Fall through.
case ISD::SETCC:
// If setcc returns 0/-1, all bits are sign bits.
- if (TLI.getSetCCResultContents() ==
- TargetLowering::ZeroOrNegativeOneSetCCResult)
+ if (TLI.getBooleanContents() ==
+ TargetLowering::ZeroOrNegativeOneBooleanContent)
return VTBits;
break;
case ISD::ROTL:
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 62a6df3259..01977908be 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -462,7 +462,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
StackPointerRegisterToSaveRestore = 0;
ExceptionPointerRegister = 0;
ExceptionSelectorRegister = 0;
- SetCCResultContents = UndefinedSetCCResult;
+ BooleanContents = UndefinedBooleanContent;
SchedPreferenceInfo = SchedulingForLatency;
JumpBufSize = 0;
JumpBufAlignment = 0;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 20:01:38 +0000