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-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp23
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp31
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp5
3 files changed, 17 insertions, 42 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index d929aaff7b..4ea29063ab 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -231,8 +231,7 @@ unsigned ScheduleDAG::getVR(SDValue Op,
void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
unsigned IIOpNum,
const TargetInstrDesc *II,
- DenseMap<SDValue, unsigned> &VRBaseMap,
- bool overlapsEarlyClobber) {
+ DenseMap<SDValue, unsigned> &VRBaseMap) {
if (Op.isMachineOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@@ -245,9 +244,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
const TargetInstrDesc &TID = MI->getDesc();
bool isOptDef = IIOpNum < TID.getNumOperands() &&
TID.OpInfo[IIOpNum].isOptionalDef();
- MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, false, false,
- false, 0, false,
- overlapsEarlyClobber));
+ MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -281,9 +278,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
const ConstantFP *CFP = F->getConstantFPValue();
MI->addOperand(MachineOperand::CreateFPImm(CFP));
} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
- MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, false,
- false, false, 0, false,
- overlapsEarlyClobber));
+ MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
} else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
@@ -319,9 +314,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addOperand(MachineOperand::CreateReg(VReg, false, false,
- false, false, 0, false,
- overlapsEarlyClobber));
+ MI->addOperand(MachineOperand::CreateReg(VReg, false));
// Verify that it is right. Note that the reg class of the physreg and the
// vreg don't necessarily need to match, but the target copy insertion has
@@ -603,7 +596,6 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
- bool overlapsEarlyClobber = false;
unsigned Flags =
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
unsigned NumVals = Flags >> 3;
@@ -626,18 +618,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
false, 0, true));
}
break;
- case 7: // Addressing mode overlapping earlyclobber.
- case 5: // Use of register overlapping earlyclobber.
- overlapsEarlyClobber = true;
- // fall through
case 1: // Use of register.
case 3: // Immediate.
case 4: // Addressing mode.
// The addressing mode has been selected, just add all of the
// operands to the machine instruction.
for (; NumVals; --NumVals, ++i)
- AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
- overlapsEarlyClobber);
+ AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
break;
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 9768021b19..43ca2364d5 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -4554,7 +4554,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, bool HasEarlyClobber,
// If this is an early clobber or tied register, our regalloc doesn't know
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
- if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
+ if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
// If there is some other early clobber and this is an input register,
// then we are forced to pre-allocate the input reg so it doesn't
// conflict with the earlyclobber.
@@ -4843,10 +4843,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
assert(OpInfo.isIndirect && "Memory output must be indirect operand");
// Add information to the INLINEASM node to know about this output.
- unsigned ResOpType = SawEarlyClobber ?
- 7 /* MEM OVERLAPS EARLYCLOBBER */ :
- 4/*MEM*/;
- AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
+ unsigned ResOpType = 4/*MEM*/ | (1<<3);
+ AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
TLI.getPointerTy()));
AsmNodeOperands.push_back(OpInfo.CallOperand);
break;
@@ -4899,8 +4897,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
assert(((NumOps & 7) == 2 /*REGDEF*/ ||
(NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
- (NumOps & 7) == 4 /*MEM*/ ||
- (NumOps & 7) == 7 /*MEM OVERLAPS EARLYCLOBBER*/) &&
+ (NumOps & 7) == 4 /*MEM*/) &&
"Skipped past definitions?");
CurOp += (NumOps>>3)+1;
}
@@ -4922,14 +4919,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// Use the produced MatchedRegs object to
MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
- MatchedRegs.AddInlineAsmOperands(SawEarlyClobber ?
- 1 /*REGUSE*/ :
- 5 /*REGUSE OVERLAPS EARLYCLOBBER*/,
- DAG, AsmNodeOperands);
+ MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
break;
} else {
- assert(((NumOps & 7) == 7/*MEM OVERLAPS EARLYCLOBBER */ ||
- (NumOps & 7) == 4) && "Unknown matching constraint!");
+ assert(((NumOps & 7) == 4) && "Unknown matching constraint!");
assert((NumOps >> 3) == 1 && "Unexpected number of operands");
// Add information to the INLINEASM node to know about this input.
AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
@@ -4964,10 +4957,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
"Memory operands expect pointer values");
// Add information to the INLINEASM node to know about this input.
- unsigned ResOpType = SawEarlyClobber ?
- 7 /* MEM OVERLAPS EARLYCLOBBER */ :
- 4/*MEM*/;
- AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
+ unsigned ResOpType = 4/*MEM*/ | (1<<3);
+ AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
TLI.getPointerTy()));
AsmNodeOperands.push_back(InOperandVal);
break;
@@ -4985,10 +4976,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
- OpInfo.AssignedRegs.AddInlineAsmOperands(SawEarlyClobber ?
- 5 /*REGUSE OVERLAPS EARLYCLOBBER*/:
- 1/*REGUSE*/,
- DAG, AsmNodeOperands);
+ OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/,
+ DAG, AsmNodeOperands);
break;
}
case InlineAsm::isClobber: {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index a91cb1fe93..afb290d822 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1115,8 +1115,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
- if ((Flags & 7) != 4 /*MEM*/ &&
- (Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) {
+ if ((Flags & 7) != 4 /*MEM*/) {
// Just skip over this operand, copying the operands verbatim.
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
i += (Flags >> 3) + 1;
@@ -1131,7 +1130,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
// Add this to the output node.
MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
- Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3),
+ Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
i += 2;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 00:44:14 +0000