diff options
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 22145122d5..c774c6878d 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4630,7 +4630,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { if ((!AfterLegalize && !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) { Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). - convertToAPInt().getZExtValue(), MVT::i32); + bitcastToAPInt().getZExtValue(), MVT::i32); return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); @@ -4639,7 +4639,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { case MVT::f64: if ((!AfterLegalize && !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) { - Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). + Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). getZExtValue(), MVT::i64); return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), @@ -4649,7 +4649,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { // Many FP stores are not made apparent until after legalize, e.g. for // argument passing. Since this is so common, custom legalize the // 64-bit integer store into two 32-bit stores. - uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); + uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); if (TLI.isBigEndian()) std::swap(Lo, Hi); diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 8874eb872f..b7311b7d9e 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -445,7 +445,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, if (!UseCP) { if (VT!=MVT::f64 && VT!=MVT::f32) assert(0 && "Invalid type expansion"); - return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), + return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), (VT == MVT::f64) ? MVT::i64 : MVT::i32); } @@ -2357,7 +2357,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { if (CFP->getValueType(0) == MVT::f32 && getTypeAction(MVT::i32) == Legal) { Tmp3 = DAG.getConstant(CFP->getValueAPF(). - convertToAPInt().zextOrTrunc(32), + bitcastToAPInt().zextOrTrunc(32), MVT::i32); Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); @@ -2365,7 +2365,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } else if (CFP->getValueType(0) == MVT::f64) { // If this target supports 64-bit registers, do a single 64-bit store. if (getTypeAction(MVT::i64) == Legal) { - Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). + Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). zextOrTrunc(64), MVT::i64); Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); @@ -2374,7 +2374,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // Otherwise, if the target supports 32-bit registers, use 2 32-bit // stores. If the target supports neither 32- nor 64-bits, this // xform is certainly not worth it. - const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); + const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -5912,7 +5912,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ case ISD::ConstantFP: { ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); if (CFP->getValueType(0) == MVT::ppcf128) { - APInt api = CFP->getValueAPF().convertToAPInt(); + APInt api = CFP->getValueAPF().bitcastToAPInt(); Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), MVT::f64); Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 45ae85c854..466eedb0db 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -93,7 +93,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) { - return DAG.getConstant(N->getValueAPF().convertToAPInt(), + return DAG.getConstant(N->getValueAPF().bitcastToAPInt(), TLI.getTypeToTransformTo(N->getValueType(0))); } @@ -586,7 +586,7 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); assert(NVT.getSizeInBits() == integerPartWidth && "Do not know how to expand this float constant!"); - APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().convertToAPInt(); + APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt(); Lo = DAG.getConstantFP(APFloat(APInt(integerPartWidth, 1, &C.getRawData()[1])), NVT); Hi = DAG.getConstantFP(APFloat(APInt(integerPartWidth, 1, |