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Diffstat (limited to 'lib/CodeGen/LLVMTargetMachine.cpp')
-rw-r--r--lib/CodeGen/LLVMTargetMachine.cpp58
1 files changed, 28 insertions, 30 deletions
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 3e69069fa9..03b5693a6a 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -114,9 +114,10 @@ EnableFastISelOption("fast-isel", cl::Hidden,
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
- Reloc::Model RM, CodeModel::Model CM)
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS) {
- CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
+ CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
AsmInfo = T.createMCAsmInfo(Triple);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and
@@ -130,11 +131,10 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
MCContext *Context = 0;
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true;
assert(Context != 0 && "Failed to get MCContext");
@@ -219,14 +219,13 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
MCContext *Ctx = 0;
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
- addCodeEmitter(PM, OptLevel, JCE);
+ addCodeEmitter(PM, JCE);
PM.add(createGCInfoDeleter());
return false; // success!
@@ -240,10 +239,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx,
raw_ostream &Out,
- CodeGenOpt::Level OptLevel,
bool DisableVerify) {
// Add common CodeGen passes.
- if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+ if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
if (hasMCSaveTempLabels())
@@ -295,7 +293,6 @@ static void printAndVerify(PassManagerBase &PM,
/// emitting to assembly files or machine code output.
///
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
bool DisableVerify,
MCContext *&OutContext) {
// Standard LLVM-Level Passes.
@@ -313,7 +310,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createVerifierPass());
// Run loop strength reduction before anything else.
- if (OptLevel != CodeGenOpt::None && !DisableLSR) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
@@ -349,12 +346,12 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
break;
}
- if (OptLevel != CodeGenOpt::None && !DisableCGP)
+ if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
- addPreISel(PM, OptLevel);
+ addPreISel(PM);
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
@@ -377,15 +374,16 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on.
- PM.add(new MachineFunctionAnalysis(*this, OptLevel));
+ PM.add(new MachineFunctionAnalysis(*this));
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
- (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
+ (getOptLevel() == CodeGenOpt::None &&
+ EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
// Ask the target for an isel.
- if (addInstSelector(PM, OptLevel))
+ if (addInstSelector(PM))
return true;
// Print the instruction selected machine code...
@@ -395,21 +393,21 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createExpandISelPseudosPass());
// Pre-ra tail duplication.
- if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
}
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
- if (OptLevel != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass());
// If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible.
PM.add(createLocalStackSlotAllocationPass());
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack
@@ -431,15 +429,15 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
}
// Run pre-ra passes.
- if (addPreRegAlloc(PM, OptLevel))
+ if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes");
// Perform register allocation.
- PM.add(createRegisterAllocator(OptLevel));
+ PM.add(createRegisterAllocator(getOptLevel()));
printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM.
- if (OptLevel != CodeGenOpt::None) {
+ if (getOptLevel() != CodeGenOpt::None) {
// FIXME: Re-enable coloring with register when it's capable of adding
// kill markers.
if (!DisableSSC)
@@ -453,7 +451,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
}
// Run post-ra passes.
- if (addPostRegAlloc(PM, OptLevel))
+ if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass());
@@ -464,23 +462,23 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM, "After PrologEpilogCodeInserter");
// Run pre-sched2 passes.
- if (addPreSched2(PM, OptLevel))
+ if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
- PM.add(createPostRAScheduler(OptLevel));
+ if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
+ PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler");
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding");
}
// Tail duplication.
- if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate");
}
@@ -490,7 +488,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs()));
- if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
+ if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
if (EnableBlockPlacement) {
// MachineBlockPlacement is an experimental pass which is disabled by
// default currently. Eventually it should subsume CodePlacementOpt, so
@@ -509,7 +507,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
}
}
- if (addPreEmitPass(PM, OptLevel))
+ if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes");
return false;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-29 19:50:30 +0000