diff options
Diffstat (limited to 'lib/CodeGen/InstrSched/InstrScheduling.cpp')
-rw-r--r-- | lib/CodeGen/InstrSched/InstrScheduling.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 392ae04d68..cf4f294155 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S, if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode())) return false; - // Finally, if the instruction preceeds the branch, we make sure the + // Finally, if the instruction precedes the branch, we make sure the // instruction can be reordered relative to the branch. We simply check // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // @@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S, bool nodeIsPredecessor) { if (nodeIsPredecessor) { - // If node is in the same basic block (i.e., preceeds brNode), + // If node is in the same basic block (i.e., precedes brNode), // remove it and all its incident edges from the graph. Make sure we // add dummy edges for pred/succ nodes that become entry/exit nodes. graph->eraseIncidentEdges(node, /*addDummyEdges*/ true); |