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-rw-r--r--include/llvm/Target/TargetInstrInfo.h25
1 files changed, 23 insertions, 2 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 919bef1e7f..d64df445b0 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -133,13 +133,34 @@ private:
AliasAnalysis *AA) const;
public:
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
+ /// isMoveInstr - Return true if the instruction is a register to register
+ /// move and return the source and dest operands and their sub-register
+ /// indices by reference.
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& SrcReg, unsigned& DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
return false;
}
+
+ /// isIdentityCopy - Return true if the instruction is a copy (or
+ /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
+ /// destination registers are the same.
+ bool isIdentityCopy(const MachineInstr &MI) const {
+ unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
+ if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+ SrcReg == DstReg)
+ return true;
+
+ if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
+ MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
+ return true;
+
+ if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
+ MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
+ return true;
+ return false;
+ }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of