diff options
| -rw-r--r-- | lib/CodeGen/TargetInstrInfoImpl.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2012-11-16-mischedcall.ll | 33 |
2 files changed, 35 insertions, 1 deletions
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index 4439192fe2..433f2ea061 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -472,7 +472,8 @@ bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI, // stack slot reference to depend on the instruction that does the // modification. const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); - if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore())) + const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI)) return true; return false; diff --git a/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll new file mode 100644 index 0000000000..e89da3d1f7 --- /dev/null +++ b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=ppc64 -enable-misched < %s | FileCheck %s +; +; PR14315: misched should not move the physreg copy of %t below the calls. + +@.str89 = external unnamed_addr constant [6 x i8], align 1 + +declare void @init() nounwind + +declare void @clock() nounwind + +; CHECK: %entry +; CHECK: fmr f31, f1 +; CHECK: bl _init +define void @s332(double %t) nounwind { +entry: + tail call void @init() + tail call void @clock() nounwind + br label %for.cond2 + +for.cond2: ; preds = %for.body4, %entry + %i.0 = phi i32 [ %inc, %for.body4 ], [ 0, %entry ] + %cmp3 = icmp slt i32 undef, 16000 + br i1 %cmp3, label %for.body4, label %L20 + +for.body4: ; preds = %for.cond2 + %cmp5 = fcmp ogt double undef, %t + %inc = add nsw i32 %i.0, 1 + br i1 %cmp5, label %L20, label %for.cond2 + +L20: ; preds = %for.body4, %for.cond2 + %index.0 = phi i32 [ -2, %for.cond2 ], [ %i.0, %for.body4 ] + unreachable +} |