diff options
| -rw-r--r-- | include/llvm/Target/TargetSchedule.td | 9 | ||||
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 2 |
3 files changed, 7 insertions, 9 deletions
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index 97ea82ab9e..307fe2d6a0 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -1,10 +1,10 @@ //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the target-independent scheduling interfaces which should @@ -19,7 +19,7 @@ // all chip sets of the target. Each functional unit is treated as a resource // during scheduling and has an affect instruction order based on availability // during a time interval. -// +// class FuncUnit; //===----------------------------------------------------------------------===// @@ -84,7 +84,7 @@ class InstrItinClass<int ops = 1> { def NoItinerary : InstrItinClass; //===----------------------------------------------------------------------===// -// Instruction itinerary data - These values provide a runtime map of an +// Instruction itinerary data - These values provide a runtime map of an // instruction itinerary class (name) to its itinerary data. // // OperandCycles are optional "cycle counts". They specify the cycle after @@ -119,6 +119,7 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages, // class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, list<InstrItinData> iid> { + int IssueWidth = 1; list<FuncUnit> FU = fu; list<Bypass> BP = bp; list<InstrItinData> IID = iid; diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index dc311b15de..f670f28b44 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Instruction Itinerary classes used for X86 +// Instruction Itinerary classes used for X86 def IIC_DEFAULT : InstrItinClass; def IIC_ALU_MEM : InstrItinClass; def IIC_ALU_NONMEM : InstrItinClass; @@ -459,6 +459,3 @@ def IIC_NOP : InstrItinClass; def GenericItineraries : ProcessorItineraries<[], [], []>; include "X86ScheduleAtom.td" - - - diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 97322044e1..81530b5f1f 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -106,7 +106,7 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_CMOV64_RM, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_CMOV64_RR, [InstrStage<1, [Port0, Port1]>] >, // set - InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, + InstrItinData<IIC_SET_M, [InstrStage<2, [Port0, Port1]>] >, InstrItinData<IIC_SET_R, [InstrStage<1, [Port0, Port1]>] >, // jcc InstrItinData<IIC_Jcc, [InstrStage<1, [Port1]>] >, |