diff options
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 17 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/addi.ll | 30 |
3 files changed, 51 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 135df75693..49048db7b4 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -32,6 +32,18 @@ def mem16_ea : Operand<i32> { } // +// RI instruction format +// + + +class F2RI16_ins<bits<5> _op, string asmstr, + InstrItinClass itin>: + FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), + !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { + let Constraints = "$rx_ = $rx"; +} + +// // Compare a register and immediate and place result in CC // Implicit use of T8 // @@ -416,6 +428,10 @@ class MayStore { // def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; +def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, + ArithLogic16Defs<0> { + let AddedComplexity = 5; +} def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, ArithLogic16Defs<0>; @@ -1055,6 +1071,7 @@ class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), (I CPU16Regs:$in, imm_type:$imm)>; +def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; def: ArithLogicI16_pat<shl, immZExt5, SllX16>; def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index c85b547d0e..052e855031 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -301,6 +301,10 @@ def HI16 : SDNodeXForm<imm, [{ // Node immediate fits as 16-bit sign extended on target immediate. // e.g. addi, andi +def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; + +// Node immediate fits as 16-bit sign extended on target immediate. +// e.g. addi, andi def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; // Node immediate fits as 15-bit sign extended on target immediate. diff --git a/test/CodeGen/Mips/addi.ll b/test/CodeGen/Mips/addi.ll new file mode 100644 index 0000000000..8f70a469c4 --- /dev/null +++ b/test/CodeGen/Mips/addi.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=16 + +@i = global i32 6, align 4 +@j = global i32 12, align 4 +@k = global i32 15, align 4 +@l = global i32 20, align 4 +@.str = private unnamed_addr constant [13 x i8] c"%i %i %i %i\0A\00", align 1 + +define void @foo() nounwind { +entry: + %0 = load i32* @i, align 4 + %add = add nsw i32 %0, 5 + store i32 %add, i32* @i, align 4 + %1 = load i32* @j, align 4 + %sub = sub nsw i32 %1, 5 + store i32 %sub, i32* @j, align 4 + %2 = load i32* @k, align 4 + %add1 = add nsw i32 %2, 10000 + store i32 %add1, i32* @k, align 4 + %3 = load i32* @l, align 4 + %sub2 = sub nsw i32 %3, 10000 + store i32 %sub2, i32* @l, align 4 +; 16: addiu ${{[0-9]+}}, 5 # 16 bit inst +; 16: addiu ${{[0-9]+}}, -5 # 16 bit inst +; 16: addiu ${{[0-9]+}}, 10000 +; 16: addiu ${{[0-9]+}}, -10000 + ret void +} + + |