diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 30 | ||||
| -rw-r--r-- | test/MC/Mips/mips-coprocessor-encodings.s | 37 |
2 files changed, 67 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index bd472d6f67..99a9f25abd 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -315,3 +315,33 @@ def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; // Instruction aliases //===----------------------------------------------------------------------===// def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; + +/// Move between CPU and coprocessor registers +let DecoderNamespace = "Mips64" in { +def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), + (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; +def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), + (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; +def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), + (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; +def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), + (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; +def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), + (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; +def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), + (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; +def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), + (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; +def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), + (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; +} +// Two operand (implicit 0 selector) versions: +def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; +def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; +def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; + diff --git a/test/MC/Mips/mips-coprocessor-encodings.s b/test/MC/Mips/mips-coprocessor-encodings.s new file mode 100644 index 0000000000..bad9163ba9 --- /dev/null +++ b/test/MC/Mips/mips-coprocessor-encodings.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding | FileCheck --check-prefix=MIPS64 %s + +# MIPS64: dmtc0 $12, $16, 2 # encoding: [0x40,0xac,0x80,0x02] +# MIPS64: dmtc0 $12, $16, 0 # encoding: [0x40,0xac,0x80,0x00] +# MIPS64: mtc0 $12, $16, 2 # encoding: [0x40,0x8c,0x80,0x02] +# MIPS64: mtc0 $12, $16, 0 # encoding: [0x40,0x8c,0x80,0x00] +# MIPS64: dmfc0 $12, $16, 2 # encoding: [0x40,0x2c,0x80,0x02] +# MIPS64: dmfc0 $12, $16, 0 # encoding: [0x40,0x2c,0x80,0x00] +# MIPS64: mfc0 $12, $16, 2 # encoding: [0x40,0x0c,0x80,0x02] +# MIPS64: mfc0 $12, $16, 0 # encoding: [0x40,0x0c,0x80,0x00] + + dmtc0 $12, $16, 2 + dmtc0 $12, $16 + mtc0 $12, $16, 2 + mtc0 $12, $16 + dmfc0 $12, $16, 2 + dmfc0 $12, $16 + mfc0 $12, $16, 2 + mfc0 $12, $16 + +# MIPS64: dmtc2 $12, $16, 2 # encoding: [0x48,0xac,0x80,0x02] +# MIPS64: dmtc2 $12, $16, 0 # encoding: [0x48,0xac,0x80,0x00] +# MIPS64: mtc2 $12, $16, 2 # encoding: [0x48,0x8c,0x80,0x02] +# MIPS64: mtc2 $12, $16, 0 # encoding: [0x48,0x8c,0x80,0x00] +# MIPS64: dmfc2 $12, $16, 2 # encoding: [0x48,0x2c,0x80,0x02] +# MIPS64: dmfc2 $12, $16, 0 # encoding: [0x48,0x2c,0x80,0x00] +# MIPS64: mfc2 $12, $16, 2 # encoding: [0x48,0x0c,0x80,0x02] +# MIPS64: mfc2 $12, $16, 0 # encoding: [0x48,0x0c,0x80,0x00] + + dmtc2 $12, $16, 2 + dmtc2 $12, $16 + mtc2 $12, $16, 2 + mtc2 $12, $16 + dmfc2 $12, $16, 2 + dmfc2 $12, $16 + mfc2 $12, $16, 2 + mfc2 $12, $16 |