diff options
| -rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 10 | ||||
| -rw-r--r-- | test/CodeGen/X86/atomic_op.ll | 11 |
4 files changed, 22 insertions, 10 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index a5d0aaa1b1..de1f014d83 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1180,7 +1180,6 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, Parent->getOpcode() != X86ISD::FP_TO_INT16_IN_MEM && Parent->getOpcode() != X86ISD::FP_TO_INT32_IN_MEM && Parent->getOpcode() != X86ISD::FP_TO_INT64_IN_MEM && - Parent->getOpcode() != X86ISD::LCMPXCHG_DAG && Parent->getOpcode() != X86ISD::FST) { unsigned AddrSpace = cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace(); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ab57353ba1..3f7f272b1b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8490,7 +8490,7 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { EVT T = Op.getValueType(); - DebugLoc dl = Op.getDebugLoc(); + DebugLoc DL = Op.getDebugLoc(); unsigned Reg = 0; unsigned size = 0; switch(T.getSimpleVT().SimpleTy) { @@ -8504,7 +8504,7 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { Reg = X86::RAX; size = 8; break; } - SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, + SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, Op.getOperand(2), SDValue()); SDValue Ops[] = { cpIn.getValue(0), Op.getOperand(1), @@ -8512,9 +8512,11 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { DAG.getTargetConstant(size, MVT::i8), cpIn.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); + MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); + SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, + Ops, 5, T, MMO); SDValue cpOut = - DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); + DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); return cpOut; } diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 9bb5f64b56..870cf74e97 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -214,10 +214,6 @@ namespace llvm { /// operand #3 optional in flag TC_RETURN, - // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. - LCMPXCHG_DAG, - LCMPXCHG8_DAG, - // FNSTCW16m - Store FP control world into i16 memory. FNSTCW16m, @@ -309,7 +305,11 @@ namespace llvm { MEMBARRIER, MFENCE, SFENCE, - LFENCE + LFENCE, + + // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. + LCMPXCHG_DAG, + LCMPXCHG8_DAG // WARNING: Do not add anything in the end unless you want the node to // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll index 677941bc60..72ff97194d 100644 --- a/test/CodeGen/X86/atomic_op.ll +++ b/test/CodeGen/X86/atomic_op.ll @@ -109,6 +109,17 @@ entry: ret void } +define void @test2(i32 addrspace(256)* nocapture %P) nounwind { +entry: +; CHECK: lock +; CEHCK: cmpxchgl %{{.*}}, %gs:(%{{.*}}) + + %0 = tail call i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* %P, i32 0, i32 1) + ret void +} + +declare i32 @llvm.atomic.cmp.swap.i32.p256i32(i32 addrspace(256)* nocapture, i32, i32) nounwind + declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind |