diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCCodeEmitter.cpp | 25 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 12 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 24 |
3 files changed, 38 insertions, 23 deletions
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index a5517f091f..952a45684a 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -61,7 +61,8 @@ namespace { const MachineOperand &MO) const; unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getCallTargetEncoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; const char *getPassName() const { return "PowerPC Machine Code Emitter"; } @@ -159,8 +160,8 @@ MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO, RelocID, MO.getIndex(), 0); } -unsigned PPCCodeEmitter::getCallTargetEncoding(const MachineInstr &MI, - unsigned OpNo) const { +unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI, + unsigned OpNo) const { const MachineOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); @@ -168,6 +169,13 @@ unsigned PPCCodeEmitter::getCallTargetEncoding(const MachineInstr &MI, return 0; } +unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI, + unsigned OpNo) const { + const MachineOperand &MO = MI.getOperand(OpNo); + MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx)); + return 0; +} + unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const { @@ -239,17 +247,6 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4); } MCE.addRelocation(R); - - } else if (MO.isMBB()) { - unsigned Reloc = 0; - unsigned Opcode = MI.getOpcode(); - if (Opcode == PPC::B) - Reloc = PPC::reloc_pcrel_bx; - else // BCC instruction - Reloc = PPC::reloc_pcrel_bcx; - - MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), - Reloc, MO.getMBB())); } else { #ifndef NDEBUG errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index ba5aab7d4f..269f371bda 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -286,11 +286,15 @@ def u16imm : Operand<i32> { def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing. let PrintMethod = "printS16X4ImmOperand"; } -def target : Operand<OtherVT> { +def directbrtarget : Operand<OtherVT> { let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getDirectBrEncoding"; +} +def condbrtarget : Operand<OtherVT> { + let EncoderMethod = "getCondBrEncoding"; } def calltarget : Operand<iPTR> { - let EncoderMethod = "getCallTargetEncoding"; + let EncoderMethod = "getDirectBrEncoding"; } def aaddr : Operand<iPTR> { let PrintMethod = "printAbsAddrOperand"; @@ -409,7 +413,7 @@ let Defs = [LR] in let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { let isBarrier = 1 in { - def B : IForm<18, 0, 0, (outs), (ins target:$dst), + def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), "b $dst", BrB, [(br bb:$dst)]>; } @@ -417,7 +421,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { // BCC represents an arbitrary conditional branch on a predicate. // FIXME: should be able to write a pattern for PPCcondbranch, but can't use // a two-value operand where a dag node expects two operands. :( - def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst), + def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), "b${cond:cc} ${cond:reg}, $dst" /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; } diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp index 67ab66537a..29cc2cabcb 100644 --- a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -58,9 +58,12 @@ public: return Infos[Kind - FirstTargetFixupKind]; } - unsigned getCallTargetEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const; - + unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const; + + unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const; @@ -96,8 +99,8 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM, } unsigned PPCMCCodeEmitter:: -getCallTargetEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixups) const { +getDirectBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); @@ -107,6 +110,17 @@ getCallTargetEncoding(const MCInst &MI, unsigned OpNo, return 0; } +unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + + + + return 0; +} + + unsigned PPCMCCodeEmitter:: get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const { |