diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 6 |
2 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ee5246675b..7cc14546da 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -760,7 +760,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { // If this is an FP return with ScalarSSE, we need to move the value from // an XMM register onto the fp-stack. - if (isTypeInSSEReg(RVLocs[0].getValVT())) { + if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { SDOperand MemLoc; // If this is a load into a scalarsse value, don't store the loaded value @@ -835,7 +835,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, // If we are using ScalarSSE, store ST(0) to the stack and reload it into // an XMM register. - if (isTypeInSSEReg(RVLocs[0].getValVT())) { + if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { SDOperand StoreLoc; const Value *SrcVal = 0; int SrcValOffset = 0; @@ -3860,7 +3860,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { StackSlot, NULL, 0); // These are really Legal; caller falls through into that case. - if (SrcVT == MVT::i32 && isTypeInSSEReg(Op.getValueType())) + if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) return Result; if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && Subtarget->is64Bit()) @@ -3868,7 +3868,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { // Build the FILD SDVTList Tys; - bool useSSE = isTypeInSSEReg(Op.getValueType()); + bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); if (useSSE) Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); else @@ -3911,7 +3911,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { // These are really Legal. if (Op.getValueType() == MVT::i32 && - isTypeInSSEReg(Op.getOperand(0).getValueType())) + isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) return std::make_pair(SDOperand(), SDOperand()); if (Subtarget->is64Bit() && Op.getValueType() == MVT::i64 && @@ -3934,7 +3934,7 @@ FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = DAG.getEntryNode(); SDOperand Value = Op.getOperand(0); - if (isTypeInSSEReg(Op.getOperand(0).getValueType())) { + if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); @@ -4166,7 +4166,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { bool IllegalFPCMov = false; if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) && - !isTypeInSSEReg(VT)) // FPStack? + !isScalarFPTypeInSSEReg(VT)) // FPStack? IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); if ((Opc == X86ISD::CMP || diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index baebfa4c12..f6bdfd0fe1 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -426,9 +426,9 @@ namespace llvm { bool X86ScalarSSEf32; bool X86ScalarSSEf64; - /// isTypeInSSEReg - Return true if the specified scalar FP type is computed - /// in an SSE register, not on the X87 floating point stack. - bool isTypeInSSEReg(MVT::ValueType VT) const { + /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is + /// computed in an SSE register, not on the X87 floating point stack. + bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const { return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 } |