diff options
| -rw-r--r-- | lib/Target/PowerPC/PPC.h | 20 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 13 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 11 |
3 files changed, 29 insertions, 15 deletions
diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h index c8ea2829c4..5d737f692b 100644 --- a/lib/Target/PowerPC/PPC.h +++ b/lib/Target/PowerPC/PPC.h @@ -28,17 +28,17 @@ namespace llvm { class MachineCodeEmitter; namespace PPC { - /// Predicate - These are "(BO << 5) | BI" for various predicates. + /// Predicate - These are "(BI << 5) | BO" for various predicates. enum Predicate { - PRED_ALWAYS = (20 << 5) | 0, - PRED_LT = (12 << 5) | 0, - PRED_LE = ( 4 << 5) | 1, - PRED_EQ = (12 << 5) | 2, - PRED_GE = ( 4 << 5) | 0, - PRED_GT = (12 << 5) | 1, - PRED_NE = ( 4 << 5) | 2, - PRED_UN = (12 << 5) | 3, - PRED_NU = ( 4 << 5) | 3 + PRED_ALWAYS = (0 << 5) | 20, + PRED_LT = (0 << 5) | 12, + PRED_LE = (1 << 5) | 4, + PRED_EQ = (2 << 5) | 12, + PRED_GE = (0 << 5) | 4, + PRED_GT = (1 << 5) | 12, + PRED_NE = (2 << 5) | 4, + PRED_UN = (3 << 5) | 12, + PRED_NU = (3 << 5) | 4 }; } diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index dd9dbc38e3..2ab9eedc85 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -399,6 +399,19 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, let Inst{31} = lk; } +class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, + dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { + bits<7> BIBO; // 2 bits of BI and 5 bits of BO. + bits<3> CR; + + let BO = BIBO{0-4}; + let BI{0-1} = BIBO{5-6}; + let BI{2-4} = CR; + let BH = 0; +} + + class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> : XLForm_2<opcode, xo, lk, OL, asmstr, itin, pattern> { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 81332c1acd..e072e7e024 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -255,9 +255,9 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. let MIOperandInfo = (ops i32imm, ptr_rc); } -// PowerPC Predicate operand. 640 = ((20<<5)|0) = always, CR0 is a dummy reg +// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg // that doesn't matter. -def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 640), CR0)> { +def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 20), CR0)> { let PrintMethod = "printPredicateOperand"; } @@ -317,9 +317,10 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler. let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in { let isReturn = 1 in - def BLR : XLForm_2_ext<19, 16, 20, 0, 0, - (ops pred:$p), - "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>; + def BLR : XLForm_2_br<19, 16, 0, + (ops pred:$p), + "b${p:cc}lr ${p:reg}", BrB, + [(retflag)]>; def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>; } |