diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 1 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-MOVs-arm.txt | 17 |
2 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 2f9da43a5b..28b53ca67c 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2009,6 +2009,7 @@ def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src), bits<4> Rd; bits<12> src; let Inst{15-12} = Rd; + let Inst{19-16} = 0b0000; let Inst{11-0} = src; let Inst{25} = 0; } diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt new file mode 100644 index 0000000000..cfbba43fd5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.88 LSL (immediate) +# A8.6.98 MOV (shifted register), and +# I.1 Instruction encoding diagrams and pseudocode +0x2 0xd1 0xbc 0xf1 + + |