4 files changed, 34 insertions, 22 deletions

diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index eacc8fc04a..c04d49ed47 100644
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -135,48 +135,26 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   switch(MI->getDesc().getOpcode()) {
   default:
     return false;
-  case Mips::BteqzT8CmpX16:
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
-    break;
   case Mips::BteqzT8CmpiX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
                            Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
     break;
-  case Mips::BteqzT8SltX16:
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
-    break;
   case Mips::BteqzT8SltiX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
                            Mips::SltiRxImm16, Mips::SltiRxImmX16);
     break;
-  case Mips::BteqzT8SltuX16:
-    // TBD: figure out a way to get this or remove the instruction
-    // altogether.
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
-    break;
   case Mips::BteqzT8SltiuX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
                            Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
     break;
-  case Mips::BtnezT8CmpX16:
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
-    break;
   case Mips::BtnezT8CmpiX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
                            Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
     break;
-  case Mips::BtnezT8SltX16:
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
-    break;
   case Mips::BtnezT8SltiX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
                            Mips::SltiRxImm16, Mips::SltiRxImmX16);
     break;
-  case Mips::BtnezT8SltuX16:
-    // TBD: figure out a way to get this or remove the instruction
-    // altogether.
-    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
-    break;
   case Mips::BtnezT8SltiuX16:
     ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
                            Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
index 1a50faff11..01be7e7137 100644
--- a/lib/Target/Mips/Mips16InstrInfo.td
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -225,6 +225,7 @@ class FEXT_T8I816_ins<string asmstr, string asmstr2>:
                !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
                !strconcat(asmstr, "\t$imm"))),[]> {
   let isCodeGenOnly=1;
+  let usesCustomInserter = 1;
 }
 
 //
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 68fa28b35b..1a0d97bf6d 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -1429,6 +1429,20 @@ MachineBasicBlock *MipsTargetLowering::EmitSeliT16
 
 }
 
+
+MachineBasicBlock
+  *MipsTargetLowering::EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
+                           MachineInstr *MI,
+                           MachineBasicBlock *BB) const {
+  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+  unsigned regX = MI->getOperand(0).getReg();
+  unsigned regY = MI->getOperand(1).getReg();
+  MachineBasicBlock *target = MI->getOperand(2).getMBB();
+  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
+  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
+  MI->eraseFromParent();   // The pseudo instruction is gone now.
+  return BB;
+}
 MachineBasicBlock *
 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
                                                 MachineBasicBlock *BB) const {
@@ -1568,6 +1582,22 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
   case Mips::SelTBtneZSltu:
     return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
+  case Mips::BteqzT8CmpX16:
+    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
+  case Mips::BteqzT8SltX16:
+    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
+  case Mips::BteqzT8SltuX16:
+    // TBD: figure out a way to get this or remove the instruction
+    // altogether.
+    return EmitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
+  case Mips::BtnezT8CmpX16:
+    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
+  case Mips::BtnezT8SltX16:
+    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
+  case Mips::BtnezT8SltuX16:
+    // TBD: figure out a way to get this or remove the instruction
+    // altogether.
+    return EmitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
   }
 }
 
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 2896de5d57..ac05c83210 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -413,6 +413,9 @@ namespace llvm {
     MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
                                   MachineInstr *MI,
                                   MachineBasicBlock *BB) const;
+    MachineBasicBlock *EmitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
+                               MachineInstr *MI,
+                               MachineBasicBlock *BB) const;
   };
 }