diff options
| -rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 7 | ||||
| -rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 12 |
2 files changed, 17 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index df9d393a8f..5a1944fd5f 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -1122,9 +1122,12 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { unsigned FreeRegInactiveCount = 0; // If copy coalescer has assigned a "preferred" register, check if it's - // available first. + // available first. Coalescer can create new earlyclobber interferences, + // so we need to check that. if (cur->preference) { - if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) { + if (prt_->isRegAvail(cur->preference) && + RC->contains(cur->preference) && + noEarlyClobberConflict(cur, cur->preference)) { DOUT << "\t\tassigned the preferred register: " << tri_->getName(cur->preference) << "\n"; return cur->preference; diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 33061890c0..88996575db 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -1206,6 +1206,14 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { DOUT << " and "; DstInt.print(DOUT, tri_); DOUT << ": "; + // If one interval is earlyclobber and the other is overlaps-earlyclobber, + // we cannot coalesce them. + if ((SrcInt.isEarlyClobber && DstInt.overlapsEarlyClobber) || + (DstInt.isEarlyClobber && SrcInt.overlapsEarlyClobber)) { + DOUT << "\t\tCannot join due to earlyclobber."; + return false; + } + // Check if it is necessary to propagate "isDead" property. if (!isExtSubReg && !isInsSubReg) { MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); @@ -1366,6 +1374,10 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { if (TargetRegisterInfo::isVirtualRegister(DstReg)) RemoveUnnecessaryKills(DstReg, *ResDstInt); + // Merge the earlyclobber bits. + ResDstInt->isEarlyClobber |= ResSrcInt->isEarlyClobber; + ResDstInt->overlapsEarlyClobber |= ResSrcInt->overlapsEarlyClobber; + if (isInsSubReg) // Avoid: // r1024 = op |