diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 |
3 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index c7f33c8a15..429c9780b4 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -25,7 +25,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == PPC::OR4 || oc == PPC::OR8 || + if (oc == PPC::OR4 || oc == PPC::OR8 || oc == PPC::VOR || oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3430fd6fd4..e6c3f16b43 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1009,6 +1009,9 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; +def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vor $vD, $vA, $vB", VecFP, + []>; def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vxor $vD, $vA, $vB", VecFP, []>; @@ -1151,6 +1154,7 @@ def : Pat<(v4i32 (load xoaddr:$src)), def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; + // Same as above, but using a temporary. FIXME: implement temporaries :) /* def : Pattern<(xor GPRC:$in, imm:$imm), diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index d55bdc7627..c8d2f3a055 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -110,6 +110,8 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); } else if (RC == PPC::CRRCRegisterClass) { BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); + } else if (RC == PPC::VRRCRegisterClass) { + BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else { std::cerr << "Attempt to copy register that is not GPR or FPR"; abort(); |