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-rw-r--r--lib/Target/ARM/ARMInstrInfo.td12
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td7
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp9
-rw-r--r--test/MC/ARM/basic-arm-instructions.s43
-rw-r--r--test/MC/ARM/basic-thumb2-instructions.s26
5 files changed, 97 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index c938c41ac2..9409f35974 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2103,6 +2103,18 @@ def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
let Inst{24-23} = 0b11;
}
+def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
+def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
+
+def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
+def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
+
+def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
+def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
+
+def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
+def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
+
// Return From Exception
class RFEI<bit wb, string asm>
: XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index cf8b3024fb..c9d709eb52 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3481,6 +3481,13 @@ def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
"srsia","\tsp, $mode", []>;
+
+def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
+def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
+
+def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
+def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
+
// Return From Exception is a system instruction.
class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c95cc1b311..6c678fdbd7 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4625,6 +4625,15 @@ bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
}
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
+
+ // There can be a trailing '!' on operands that we want as a separate
+ // '!' Token operand. Handle that here. For example, the compatibilty
+ // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
+ if (Parser.getTok().is(AsmToken::Exclaim)) {
+ Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
+ Parser.getTok().getLoc()));
+ Parser.Lex(); // Eat exclaim token
+ }
return false;
}
// w/ a ':' after the '#', it's just like a plain ':'.
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 5c2a214598..45ea278aac 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -2087,6 +2087,49 @@ Lforward:
@ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8]
@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8]
+@ Compatibility aliases.
+ srsda #5
+ srsdb #1
+ srsia #0
+ srsib #15
+
+ srsda #31!
+ srsdb #19!
+ srsia #2!
+ srsib #14!
+
+ srsfa #11
+ srsea #10
+ srsfd #9
+ srsed #5
+
+ srsfa #5!
+ srsea #5!
+ srsfd #5!
+ srsed #5!
+
+ srs #5
+ srs #5!
+
+@ CHECK: srsda sp, #5 @ encoding: [0x05,0x05,0x4d,0xf8]
+@ CHECK: srsdb sp, #1 @ encoding: [0x01,0x05,0x4d,0xf9]
+@ CHECK: srsia sp, #0 @ encoding: [0x00,0x05,0xcd,0xf8]
+@ CHECK: srsib sp, #15 @ encoding: [0x0f,0x05,0xcd,0xf9]
+@ CHECK: srsda sp!, #31 @ encoding: [0x1f,0x05,0x6d,0xf8]
+@ CHECK: srsdb sp!, #19 @ encoding: [0x13,0x05,0x6d,0xf9]
+@ CHECK: srsia sp!, #2 @ encoding: [0x02,0x05,0xed,0xf8]
+@ CHECK: srsib sp!, #14 @ encoding: [0x0e,0x05,0xed,0xf9]
+@ CHECK: srsda sp, #11 @ encoding: [0x0b,0x05,0x4d,0xf8]
+@ CHECK: srsdb sp, #10 @ encoding: [0x0a,0x05,0x4d,0xf9]
+@ CHECK: srsia sp, #9 @ encoding: [0x09,0x05,0xcd,0xf8]
+@ CHECK: srsib sp, #5 @ encoding: [0x05,0x05,0xcd,0xf9]
+@ CHECK: srsda sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf8]
+@ CHECK: srsdb sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf9]
+@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8]
+@ CHECK: srsib sp!, #5 @ encoding: [0x05,0x05,0xed,0xf9]
+@ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8]
+@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8]
+
@------------------------------------------------------------------------------
@ SSAT
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index d495c91c0e..9278a2a94b 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -2352,6 +2352,32 @@ _func:
@ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0]
@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0]
+ srsdb #1
+ srsia #0
+
+ srsdb #19!
+ srsia #2!
+
+ srsea #10
+ srsfd #9
+
+ srsea #5!
+ srsfd #5!
+
+ srs #5
+ srs #5!
+
+@ CHECK: srsdb sp, #1 @ encoding: [0x0d,0xe8,0x01,0xc0]
+@ CHECK: srsia sp, #0 @ encoding: [0x8d,0xe9,0x00,0xc0]
+@ CHECK: srsdb sp!, #19 @ encoding: [0x2d,0xe8,0x13,0xc0]
+@ CHECK: srsia sp!, #2 @ encoding: [0xad,0xe9,0x02,0xc0]
+@ CHECK: srsdb sp, #10 @ encoding: [0x0d,0xe8,0x0a,0xc0]
+@ CHECK: srsia sp, #9 @ encoding: [0x8d,0xe9,0x09,0xc0]
+@ CHECK: srsdb sp!, #5 @ encoding: [0x2d,0xe8,0x05,0xc0]
+@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0]
+@ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0]
+@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0]
+
@------------------------------------------------------------------------------
@ SSAT
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-22 02:32:22 +0000