diff options
| -rw-r--r-- | include/llvm/Intrinsics.td | 1 | ||||
| -rw-r--r-- | include/llvm/IntrinsicsXCore.td | 14 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/XCore/bitrev.ll | 8 | ||||
| -rw-r--r-- | test/CodeGen/XCore/getid.ll | 8 |
6 files changed, 35 insertions, 5 deletions
diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index d14961a08a..c654c10eb8 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -411,3 +411,4 @@ include "llvm/IntrinsicsX86.td" include "llvm/IntrinsicsARM.td" include "llvm/IntrinsicsCellSPU.td" include "llvm/IntrinsicsAlpha.td" +include "llvm/IntrinsicsXCore.td" diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td new file mode 100644 index 0000000000..a86cda28a5 --- /dev/null +++ b/include/llvm/IntrinsicsXCore.td @@ -0,0 +1,14 @@ +//==- IntrinsicsXCore.td - XCore intrinsics -*- tablegen -*-==// +// +// Copyright (C) 2008 XMOS +// +//===----------------------------------------------------------------------===// +// +// This file defines all of the XCore-specific intrinsics. +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". + def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; + def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; +} diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 96b1ae7c5d..765e6182b8 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -226,9 +226,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) } static inline SDValue BuildGetId(SelectionDAG &DAG) { - // TODO - assert(0 && "Unimplemented"); - return SDValue(); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32, + DAG.getConstant(Intrinsic::xcore_getid, MVT::i32)); } static inline bool isZeroLengthArray(const Type *Ty) { diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 15e51f51b1..031ad875fa 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -750,7 +750,7 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), // getd, testlcl, tinitlr, getps, setps def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), "bitrev $dst, $src", - []>; + [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), "byterev $dst, $src", @@ -790,7 +790,7 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), let Defs = [R11] in def GETID_0R : _F0R<(outs), (ins), "get r11, id", - []>; + [(set R11, (int_xcore_getid))]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns diff --git a/test/CodeGen/XCore/bitrev.ll b/test/CodeGen/XCore/bitrev.ll new file mode 100644 index 0000000000..38f3948697 --- /dev/null +++ b/test/CodeGen/XCore/bitrev.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep bitrev %t1.s | count 1 +declare i32 @llvm.xcore.bitrev(i32) + +define i32 @test(i32 %val) { + %result = call i32 @llvm.xcore.bitrev(i32 %val) + ret i32 %result +} diff --git a/test/CodeGen/XCore/getid.ll b/test/CodeGen/XCore/getid.ll new file mode 100644 index 0000000000..810e8ad6e7 --- /dev/null +++ b/test/CodeGen/XCore/getid.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=xcore > %t1.s +; RUN: grep "get r11, id" %t1.s | count 1 +declare i32 @llvm.xcore.getid() + +define i32 @test() { + %result = call i32 @llvm.xcore.getid() + ret i32 %result +} |