diff options
| -rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 29 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 3 |
2 files changed, 21 insertions, 11 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index e65af677f8..f0cb95f39b 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -713,17 +713,26 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, Imm12 = 0; isAdd = false ; // 'U' bit is set as part of the fixup. - assert(MO.isExpr() && "Unexpected machine operand type!"); - const MCExpr *Expr = MO.getExpr(); + if (MO.isExpr()) { + const MCExpr *Expr = MO.getExpr(); - MCFixupKind Kind; - if (isThumb2()) - Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); - else - Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); - - ++MCNumCPRelocations; + MCFixupKind Kind; + if (isThumb2()) + Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); + else + Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + + ++MCNumCPRelocations; + } else { + Reg = ARM::PC; + int32_t Offset = MO.getImm(); + if (Offset < 0) { + Offset *= -1; + isAdd = false; + } + Imm12 = Offset; + } } else isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 8a4f6fc05c..d7df77735b 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -850,10 +850,11 @@ _func: @ LDRSH(literal) @------------------------------------------------------------------------------ ldrsh r5, _bar + ldrsh.w r4, #1435 @ CHECK: ldrsh.w r5, _bar @ encoding: [0xbf'A',0xf9'A',A,0x50'A'] @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 - +@ CHECK: ldrsh.w r4, #1435 @ encoding: [0x3f,0xf9,0x9b,0x45] @------------------------------------------------------------------------------ @ LDRSHT |