diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2012-08-30-select.ll | 2 |
2 files changed, 5 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index c334f1fba5..18a71691d4 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -475,10 +475,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { // What is the size of each element in the vector mask. EVT BitTy = MaskTy.getScalarType(); - // Turn the mask into an all-one or all-zero word. - Mask = DAG.getAnyExtOrTrunc(Mask, DL, BitTy); - Mask = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, BitTy, Mask, - DAG.getValueType(MVT::i1)); + Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask, + DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy), + DAG.getConstant(3, BitTy)); // Broadcast the mask so that the entire vector is all-one or all zero. SmallVector<SDValue, 8> Ops(NumElem, Mask); diff --git a/test/CodeGen/ARM/2012-08-30-select.ll b/test/CodeGen/ARM/2012-08-30-select.ll index 8021533b1b..4c94ac9dbf 100644 --- a/test/CodeGen/ARM/2012-08-30-select.ll +++ b/test/CodeGen/ARM/2012-08-30-select.ll @@ -2,6 +2,8 @@ ; rdar://12201387 ;CHECK: select_s_v_v +;CHECK: it eq +;CHECK-NEXT: moveq.w r2, #-1 ;CHECK: vbsl ;CHECK: bx define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) { |