diff options
77 files changed, 903 insertions, 875 deletions
diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index f56c053e47..6e08f7b050 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -345,7 +345,7 @@ public: /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead /// of `new MachineInstr'. /// - MachineInstr *CreateMachineInstr(const TargetInstrDesc &TID, + MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp = false); diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index c36dd69e2d..07a14cf0c1 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -17,7 +17,7 @@ #define LLVM_CODEGEN_MACHINEINSTR_H #include "llvm/CodeGen/MachineOperand.h" -#include "llvm/Target/TargetInstrDesc.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/Target/TargetOpcodes.h" #include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist_node.h" @@ -30,7 +30,6 @@ namespace llvm { template <typename T> class SmallVectorImpl; class AliasAnalysis; -class TargetInstrDesc; class TargetInstrInfo; class TargetRegisterInfo; class MachineFunction; @@ -57,7 +56,7 @@ public: // function frame setup code. }; private: - const TargetInstrDesc *TID; // Instruction descriptor. + const MCInstrDesc *MCID; // Instruction descriptor. uint16_t NumImplicitOps; // Number of implicit operands (which // are determined at construction time). @@ -94,7 +93,7 @@ private: MachineInstr(MachineFunction &, const MachineInstr &); /// MachineInstr ctor - This constructor creates a dummy MachineInstr with - /// TID NULL and no operands. + /// MCID NULL and no operands. MachineInstr(); // The next two constructors have DebugLoc and non-DebugLoc versions; @@ -103,25 +102,25 @@ private: /// MachineInstr ctor - This constructor creates a MachineInstr and adds the /// implicit operands. It reserves space for the number of operands specified - /// by the TargetInstrDesc. The version with a DebugLoc should be preferred. - explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); + /// by the MCInstrDesc. The version with a DebugLoc should be preferred. + explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic /// block. The version with a DebugLoc should be preferred. - MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); + MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID); /// MachineInstr ctor - This constructor create a MachineInstr and add the /// implicit operands. It reserves space for number of operands specified by - /// TargetInstrDesc. An explicit DebugLoc is supplied. - explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, + /// MCInstrDesc. An explicit DebugLoc is supplied. + explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = false); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic /// block. MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, - const TargetInstrDesc &TID); + const MCInstrDesc &MCID); ~MachineInstr(); @@ -183,11 +182,11 @@ public: /// getDesc - Returns the target instruction descriptor of this /// MachineInstr. - const TargetInstrDesc &getDesc() const { return *TID; } + const MCInstrDesc &getDesc() const { return *MCID; } /// getOpcode - Returns the opcode of this MachineInstr. /// - int getOpcode() const { return TID->Opcode; } + int getOpcode() const { return MCID->Opcode; } /// Access to explicit operands of the instruction. /// @@ -464,8 +463,8 @@ public: /// hasUnmodeledSideEffects - Return true if this instruction has side /// effects that are not modeled by mayLoad / mayStore, etc. - /// For all instructions, the property is encoded in TargetInstrDesc::Flags - /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is + /// For all instructions, the property is encoded in MCInstrDesc::Flags + /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is /// INLINEASM instruction, in which case the side effect property is encoded /// in one of its operands (see InlineAsm::Extra_HasSideEffect). /// @@ -497,7 +496,7 @@ public: /// setDesc - Replace the instruction descriptor (thus opcode) of /// the current instruction with a new one. /// - void setDesc(const TargetInstrDesc &tid) { TID = &tid; } + void setDesc(const MCInstrDesc &tid) { MCID = &tid; } /// setDebugLoc - Replace current source information with new such. /// Avoid using this, the constructor argument is preferable. diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 1c48af952d..b989027246 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -22,7 +22,7 @@ namespace llvm { -class TargetInstrDesc; +class MCInstrDesc; class MDNode; namespace RegState { @@ -180,8 +180,8 @@ public: /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, - const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)); + const MCInstrDesc &MCID) { + return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)); } /// BuildMI - This version of the builder sets up the first operand as a @@ -189,9 +189,9 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF, /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)) + return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)) .addReg(DestReg, RegState::Define); } @@ -202,9 +202,9 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF, inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); + MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); } @@ -216,8 +216,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, - const TargetInstrDesc &TID) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); + const MCInstrDesc &MCID) { + MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI); } @@ -228,8 +228,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, - const TargetInstrDesc &TID) { - return BuildMI(*BB, BB->end(), DL, TID); + const MCInstrDesc &MCID) { + return BuildMI(*BB, BB->end(), DL, MCID); } /// BuildMI - This version of the builder inserts the newly-built @@ -238,9 +238,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - return BuildMI(*BB, BB->end(), DL, TID, DestReg); + return BuildMI(*BB, BB->end(), DL, MCID, DestReg); } inline unsigned getDefRegState(bool B) { diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 0657664b18..1bbc6c54d7 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -34,7 +34,7 @@ namespace llvm { class ScheduleDAG; class SDNode; class TargetInstrInfo; - class TargetInstrDesc; + class MCInstrDesc; class TargetMachine; class TargetRegisterClass; template<class Graph> class GraphWriter; @@ -507,9 +507,9 @@ namespace llvm { virtual ~ScheduleDAG(); - /// getInstrDesc - Return the TargetInstrDesc of this SUnit. + /// getInstrDesc - Return the MCInstrDesc of this SUnit. /// Return NULL for SDNodes without a machine opcode. - const TargetInstrDesc *getInstrDesc(const SUnit *SU) const { + const MCInstrDesc *getInstrDesc(const SUnit *SU) const { if (SU->isInstr()) return &SU->getInstr()->getDesc(); return getNodeDesc(SU->getNode()); } @@ -579,8 +579,8 @@ namespace llvm { void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); private: - // Return the TargetInstrDesc of this SDNode or NULL. - const TargetInstrDesc *getNodeDesc(const SDNode *Node) const; + // Return the MCInstrDesc of this SDNode or NULL. + const MCInstrDesc *getNodeDesc(const SDNode *Node) const; }; class SUnitIterator : public std::iterator<std::forward_iterator_tag, diff --git a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h index 118df28abb..060e89a3fd 100644 --- a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h +++ b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h @@ -25,7 +25,6 @@ namespace llvm { class InstrItineraryData; -class TargetInstrDesc; class ScheduleDAG; class SUnit; diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/MC/MCInstrDesc.h index 6a540ab7cb..5d0779a12a 100644 --- a/include/llvm/Target/TargetInstrDesc.h +++ b/include/llvm/MC/MCInstrDesc.h @@ -1,4 +1,4 @@ -//===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===// +//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,26 +7,23 @@ // //===----------------------------------------------------------------------===// // -// This file defines the TargetOperandInfo and TargetInstrDesc classes, which +// This file defines the McOperandInfo and McInstrDesc classes, which // are used to describe target instructions and their operands. // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETINSTRDESC_H -#define LLVM_TARGET_TARGETINSTRDESC_H +#ifndef LLVM_MC_MCINSTRDESC_H +#define LLVM_MC_MCINSTRDESC_H #include "llvm/Support/DataTypes.h" namespace llvm { -class TargetRegisterClass; -class TargetRegisterInfo; - //===----------------------------------------------------------------------===// // Machine Operand Flags and Description //===----------------------------------------------------------------------===// -namespace TOI { +namespace MCOI { // Operand constraints enum OperandConstraint { TIED_TO = 0, // Must be allocated the same register as. @@ -34,7 +31,7 @@ namespace TOI { }; /// OperandFlags - These are flags set on operands, but should be considered - /// private, all access should go through the TargetOperandInfo accessors. + /// private, all access should go through the MCOperandInfo accessors. /// See the accessors for a description of what these are. enum OperandFlags { LookupPtrRegClass = 0, @@ -43,10 +40,10 @@ namespace TOI { }; } -/// TargetOperandInfo - This holds information about one operand of a machine +/// MCOperandInfo - This holds information about one operand of a machine /// instruction, indicating the register class for register operands, etc. /// -class TargetOperandInfo { +class MCOperandInfo { public: /// RegClass - This specifies the register class enumeration of the operand /// if the operand is a register. If isLookupPtrRegClass is set, then this is @@ -54,7 +51,7 @@ public: /// get a dynamic register class. short RegClass; - /// Flags - These are flags from the TOI::OperandFlags enum. + /// Flags - These are flags from the MCOI::OperandFlags enum. unsigned short Flags; /// Lower 16 bits are used to specify which constraints are set. The higher 16 @@ -64,15 +61,15 @@ public: /// isLookupPtrRegClass - Set if this operand is a pointer value and it /// requires a callback to look up its register class. - bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);} + bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);} /// isPredicate - Set if this is one of the operands that made up of /// the predicate operand that controls an isPredicable() instruction. - bool isPredicate() const { return Flags & (1 << TOI::Predicate); } + bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } /// isOptionalDef - Set if this operand is a optional def. /// - bool isOptionalDef() const { return Flags & (1 << TOI::OptionalDef); } + bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } }; @@ -80,11 +77,11 @@ public: // Machine Instruction Flags and Description //===----------------------------------------------------------------------===// -/// TargetInstrDesc flags - These should be considered private to the -/// implementation of the TargetInstrDesc class. Clients should use the -/// predicate methods on TargetInstrDesc, not use these directly. These -/// all correspond to bitfields in the TargetInstrDesc::Flags field. -namespace TID { +/// MCInstrDesc flags - These should be considered private to the +/// implementation of the MCInstrDesc class. Clients should use the predicate +/// methods on MCInstrDesc, not use these directly. These all correspond to +/// bitfields in the MCInstrDesc::Flags field. +namespace MCID { enum { Variadic = 0, HasOptionalDef, @@ -114,12 +111,12 @@ namespace TID { }; } -/// TargetInstrDesc - Describe properties that are true of each -/// instruction in the target description file. This captures information about -/// side effects, register use and many other things. There is one instance of -/// this struct for each target instruction class, and the MachineInstr class -/// points to this struct directly to describe itself. -class TargetInstrDesc { +/// MCInstrDesc - Describe properties that are true of each instruction in the +/// target description file. This captures information about side effects, +/// register use and many other things. There is one instance of this struct +/// for each target instruction class, and the MachineInstr class points to +/// this struct directly to describe itself. +class MCInstrDesc { public: unsigned short Opcode; // The opcode number unsigned short NumOperands; // Num of args (may be more if vari |