diff options
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 13 |
2 files changed, 17 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index d2e1df13f9..ef93e1da55 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -384,7 +384,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [2, 1]>, // // Double-precision FP Load // use A8_Issue to enforce the 1 load/store per cycle limit @@ -393,7 +394,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [2, 1]>, // // FP Load Multiple // use A8_Issue to enforce the 1 load/store per cycle limit @@ -409,7 +411,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [1, 1]>, // // Double-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit @@ -418,7 +421,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], + [1, 1]>, // // FP Store Multiple // use A8_Issue to enforce the 1 load/store per cycle limit diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 8acc172668..729c96215a 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -482,13 +482,16 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // Double-precision FP Load + // FIXME: Result latency is 1 if address is 64-bit aligned. InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [2, 1]>, // // FP Load Multiple InstrItinData<IIC_fpLoadm, [InstrStage<1, [A9_DRegsVFP], 0, Required>, @@ -500,13 +503,15 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // Double-precision FP Store InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_Pipe1], 0>, - InstrStage<1, [A9_MUX0, A9_NPipe]>]>, + InstrStage<1, [A9_MUX0, A9_NPipe]>], + [1, 1]>, // // FP Store Multiple InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>, |