diff options
| -rw-r--r-- | lib/Target/Mips/Mips.td | 16 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.h | 32 |
3 files changed, 45 insertions, 8 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index bb83fc07c2..79c1890246 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -49,6 +49,16 @@ def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", "Enable 'signext in register' instructions.">; +def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", + "Enable 'conditional move' instructions.">; +def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", + "Enable 'multiply add/sub' instructions.">; +def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true", + "Enable 'min/max' instructions.">; +def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", + "Enable 'byte/half swap' instructions.">; +def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", + "Enable 'count leading bits' instructions.">; //===----------------------------------------------------------------------===// // Mips processors supported. @@ -65,9 +75,11 @@ def : Proc<"mips2", [FeatureMips2]>; def : Proc<"r6000", [FeatureMips2]>; // Allegrex is a 32bit subset of r4000, both for interger and fp registers, -// but much more similar to Mips2 than Mips3. +// but much more similar to Mips2 than Mips3. It also contains some of +// Mips32/Mips32r2 instructions and a custom vector fpu processor. def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, - FeatureSEInReg, FeatureVFPU]>; + FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd, + FeatureMinMax, FeatureSwap, FeatureBitCount]>; def Mips : Target { let InstructionSet = MipsInstrInfo; diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index bc87e4ba7a..29d869b8bd 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -29,8 +29,9 @@ cl::opt<unsigned> SSThreshold("mips-ssection-threshold", cl::Hidden, MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M, const std::string &FS, bool little) : MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), - IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasSEInReg(false), - HasABICall(true), HasAbsoluteCall(false), IsLinux(true) + IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasABICall(true), + HasAbsoluteCall(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), + HasMulDivAdd(false), HasMinMax(false), HasSwap(false), HasBitCount(false) { std::string CPU = "mips1"; diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index c3a03e3bcd..656199a69a 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -58,9 +58,6 @@ protected: // HasVFPU - Processor has a vector floating point unit. bool HasVFPU; - // HasSEInReg - Target has SEB and SEH (signext in register) instructions. - bool HasSEInReg; - // IsABICall - Enable SRV4 code for SVR4-style dynamic objects bool HasABICall; @@ -75,6 +72,27 @@ protected: // bytes into the small data or bss section. The default is 8. unsigned SSectionThreshold; + /// Features related to the presence of specific instructions. + + // HasSEInReg - SEB and SEH (signext in register) instructions. + bool HasSEInReg; + + // HasCondMov - Conditional mov (MOVZ, MOVN) instructions. + bool HasCondMov; + + // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu) + // instructions. + bool HasMulDivAdd; + + // HasMinMax - MIN and MAX instructions. + bool HasMinMax; + + // HasSwap - Byte and half swap instructions. + bool HasSwap; + + // HasBitCount - Count leading '1' and '0' bits. + bool HasBitCount; + InstrItineraryData InstrItins; public: @@ -102,12 +120,18 @@ public: bool isSingleFloat() const { return IsSingleFloat; }; bool isNotSingleFloat() const { return !IsSingleFloat; }; bool hasVFPU() const { return HasVFPU; }; - bool hasSEInReg() const { return HasSEInReg; }; bool hasABICall() const { return HasABICall; }; bool hasAbsoluteCall() const { return HasAbsoluteCall; }; bool isLinux() const { return IsLinux; }; unsigned getSSectionThreshold() const { return SSectionThreshold; } + /// Features related to the presence of specific instructions. + bool hasSEInReg() const { return HasSEInReg; }; + bool hasCondMov() const { return HasCondMov; }; + bool hasMulDivAdd() const { return HasMulDivAdd; }; + bool hasMinMax() const { return HasMinMax; }; + bool hasSwap() const { return HasSwap; }; + bool hasBitCount() const { return HasBitCount; }; }; } // End llvm namespace |