diff options
| -rw-r--r-- | lib/Target/ARM/ARM.h | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 11 |
3 files changed, 13 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 1f0a240f75..62f2a0d2ee 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -23,7 +23,8 @@ namespace llvm { // Enums corresponding to ARM condition codes namespace ARMCC { enum CondCodes { - NE + NE, + EQ }; } @@ -31,6 +32,7 @@ namespace llvm { switch (CC) { default: assert(0 && "Unknown condition code"); case ARMCC::NE: return "ne"; + case ARMCC::EQ: return "eq"; } } diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index ee8786dc51..75253b92cd 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -84,6 +84,7 @@ static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) { switch (CC) { default: assert(0 && "Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; + case ISD::SETEQ: return ARMCC::EQ; } } @@ -317,11 +318,10 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); SDOperand TrueVal = Op.getOperand(2); SDOperand FalseVal = Op.getOperand(3); - - assert(CC == ISD::SETEQ); + SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32); SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); - return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp); + return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp); } static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 2485b10043..0b47581f84 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -54,7 +54,10 @@ def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; -def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>; + +def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>; + +def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>; def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>; @@ -111,9 +114,9 @@ def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>; let isTwoAddress = 1 in { - def moveq : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true), - "moveq $dst, $true", - [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>; + def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc), + "mov$cc $dst, $true", + [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>; } def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc), |