diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 2 |
6 files changed, 11 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 1e48108e2a..3d78851706 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2882,7 +2882,6 @@ def BCCZi64 : PseudoInst<(outs), // the normal MOV instructions. That would fix the dependency on // special casing them in tblgen. let neverHasSideEffects = 1 in { -let isAsCheapAsAMove = 1 in def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm, IIC_iCMOVr, "mov", "\t$Rd, $Rm", [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, @@ -2911,7 +2910,6 @@ def MOVCCs : AI1<0b1101, (outs GPR:$Rd), let Inst{11-0} = shift; } -let isAsCheapAsAMove = 1 in def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", @@ -2927,7 +2925,6 @@ def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm:$imm), let Inst{11-0} = imm{11-0}; } -let isAsCheapAsAMove = 1 in def MOVCCi : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi, "mov", "\t$Rd, $imm", @@ -2945,9 +2942,8 @@ def MOVCCi : AI1<0b1101, (outs GPR:$Rd), // Two instruction predicate mov immediate. def MOVCCi32imm : PseudoInst<(outs GPR:$Rd), (ins GPR:$false, i32imm:$src, pred:$p), - IIC_iMOVix2, "", []>, RegConstraint<"$false = $Rd">; + IIC_iCMOVix2, "", []>, RegConstraint<"$false = $Rd">; -let isAsCheapAsAMove = 1 in def MVNCCi : AI1<0b1111, (outs GPR:$Rd), (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi, "mvn", "\t$Rd, $imm", diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 6fd814af2e..d058fdcf52 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2244,7 +2244,6 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq", // FIXME: should be able to write a pattern for ARMcmov, but can't use // a two-value operand where a dag node expects two operands. :( let neverHasSideEffects = 1 in { -let isAsCheapAsAMove = 1 in def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, "mov", ".w\t$dst, $true", [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>, @@ -2258,7 +2257,6 @@ def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, let Inst{7-4} = 0b0000; } -let isAsCheapAsAMove = 1 in def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), IIC_iCMOVi, "mov", ".w\t$dst, $true", [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, @@ -2271,7 +2269,6 @@ def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), let Inst{15} = 0; } -let isAsCheapAsAMove = 1 in def t2MOVCCi16 : T2I<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src), IIC_iCMOVi, "movw", "\t$dst, $src", []>, @@ -2285,9 +2282,8 @@ def t2MOVCCi16 : T2I<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src), def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst), (ins rGPR:$false, i32imm:$src, pred:$p), - IIC_iMOVix2, "", []>, RegConstraint<"$false = $dst">; + IIC_iCMOVix2, "", []>, RegConstraint<"$false = $dst">; -let isAsCheapAsAMove = 1 in def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), IIC_iCMOVi, "mvn", ".w\t$dst, $true", [/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true, diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 173961875e..2cdf3a4ddc 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -46,6 +46,7 @@ def IIC_iCMOVi : InstrItinClass; def IIC_iCMOVr : InstrItinClass; def IIC_iCMOVsi : InstrItinClass; def IIC_iCMOVsr : InstrItinClass; +def IIC_iCMOVix2 : InstrItinClass; def IIC_iMUL16 : InstrItinClass; def IIC_iMAC16 : InstrItinClass; def IIC_iMUL32 : InstrItinClass; diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index fc62faa09a..bd5e2749ea 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -77,6 +77,8 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, + InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>, // // MVN instructions InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index bc325b1ec4..4a398c4656 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -149,6 +149,10 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, + InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<1, [A9_ALU0, A9_ALU1]>, + InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>, // Integer multiply pipeline // diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index e4e9c13bd9..4c0e496942 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -70,6 +70,8 @@ def ARMV6Itineraries : ProcessorItineraries< InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>, InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>, InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, + InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>, + InstrStage<1, [V6_Pipe]>], [4]>, // // MVN instructions InstrItinData<IIC_iMVNi , [InstrStage<1, [V6_Pipe]>], [2]>, |