diff options
| -rw-r--r-- | include/llvm/CodeGen/RuntimeLibcalls.h | 1 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 3 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 30 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 1 |
5 files changed, 33 insertions, 6 deletions
diff --git a/include/llvm/CodeGen/RuntimeLibcalls.h b/include/llvm/CodeGen/RuntimeLibcalls.h index 0138b0c484..9452d9ed62 100644 --- a/include/llvm/CodeGen/RuntimeLibcalls.h +++ b/include/llvm/CodeGen/RuntimeLibcalls.h @@ -97,6 +97,7 @@ namespace RTLIB { FPTOSINT_F64_I32, FPTOSINT_F64_I64, FPTOSINT_F64_I128, + FPTOSINT_F80_I32, FPTOSINT_F80_I64, FPTOSINT_F80_I128, FPTOSINT_PPCF128_I32, diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index eddce0f817..80502cfe69 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3770,6 +3770,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { LC = RTLIB::FPTOSINT_F32_I32; else if (OVT == MVT::f64) LC = RTLIB::FPTOSINT_F64_I32; + else if (OVT == MVT::f80) + LC = RTLIB::FPTOSINT_F80_I32; + else if (OVT == MVT::ppcf128) + LC = RTLIB::FPTOSINT_PPCF128_I32; else assert(0 && "Unexpected i32-to-fp conversion!"); } else if (VT == MVT::i64) { diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index c26cb154bf..2773e8b245 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -536,6 +536,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) { case MVT::f64: LC = RTLIB::FPTOSINT_F64_I32; break; + case MVT::f80: + LC = RTLIB::FPTOSINT_F80_I32; + break; case MVT::ppcf128: LC = RTLIB::FPTOSINT_PPCF128_I32; break; diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index f633159a3d..bde61ad81a 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -444,6 +444,7 @@ SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { return Tmp; } + //===----------------------------------------------------------------------===// // Integer Operand Promotion //===----------------------------------------------------------------------===// @@ -995,7 +996,17 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo, MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i64) { + + if (VT == MVT::i32) { + if (Op.getValueType() == MVT::f32) + LC = RTLIB::FPTOSINT_F32_I32; + else if (Op.getValueType() == MVT::f64) + LC = RTLIB::FPTOSINT_F64_I32; + else if (Op.getValueType() == MVT::f80) + LC = RTLIB::FPTOSINT_F80_I32; + else if (Op.getValueType() == MVT::ppcf128) + LC = RTLIB::FPTOSINT_PPCF128_I32; + } else if (VT == MVT::i64) { if (Op.getValueType() == MVT::f32) LC = RTLIB::FPTOSINT_F32_I64; else if (Op.getValueType() == MVT::f64) @@ -1013,9 +1024,8 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo, LC = RTLIB::FPTOSINT_F80_I128; else if (Op.getValueType() == MVT::ppcf128) LC = RTLIB::FPTOSINT_PPCF128_I128; - } else { - assert(0 && "Unexpected fp-to-sint conversion!"); } + assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); } @@ -1024,7 +1034,16 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo, MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i64) { + if (VT == MVT::i32) { + if (Op.getValueType() == MVT::f32) + LC = RTLIB::FPTOUINT_F32_I32; + else if (Op.getValueType() == MVT::f64) + LC = RTLIB::FPTOUINT_F64_I32; + else if (Op.getValueType() == MVT::f80) + LC = RTLIB::FPTOUINT_F80_I32; + else if (Op.getValueType() == MVT::ppcf128) + LC = RTLIB::FPTOUINT_PPCF128_I32; + } else if (VT == MVT::i64) { if (Op.getValueType() == MVT::f32) LC = RTLIB::FPTOUINT_F32_I64; else if (Op.getValueType() == MVT::f64) @@ -1042,9 +1061,8 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo, LC = RTLIB::FPTOUINT_F80_I128; else if (Op.getValueType() == MVT::ppcf128) LC = RTLIB::FPTOUINT_PPCF128_I128; - } else { - assert(0 && "Unexpected fp-to-uint conversion!"); } + assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index ae9b917f1b..18e1c87943 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -95,6 +95,7 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; + Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; |