diff options
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.h | 8 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 2 |
2 files changed, 9 insertions, 1 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index 82f10270db..95d44afe37 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -181,6 +181,14 @@ namespace llvm { virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; + + /// After allocating this many registers, the allocator should feel + /// register pressure. The value is a somewhat random guess, based on the + /// number of non callee saved registers in the C calling convention. + virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, + MachineFunction &MF) const{ + return 50; + } }; } diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 7794f9d445..6e06e47c49 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -416,7 +416,7 @@ multiclass ImmLoadAddress def lo: ILARegInst<R32C, symbolLo, imm18>; def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val), - [/* no pattern */]>; + [(set R32C:$rT, imm18:$val)]>; } defm ILA : ImmLoadAddress; |