diff options
| -rw-r--r-- | lib/Target/XCore/XCoreISelDAGToDAG.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.h | 3 | ||||
| -rw-r--r-- | test/CodeGen/XCore/mul64.ll | 5 |
4 files changed, 14 insertions, 7 deletions
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 12967d42de..29a6ab77d0 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -220,6 +220,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, Ops, 4); } + case XCoreISD::LMUL: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), + N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, + Ops, 4); + } // Other cases are autogenerated. } } diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 70ceadd4df..d27adf40f6 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const case XCoreISD::RETSP : return "XCoreISD::RETSP"; case XCoreISD::LADD : return "XCoreISD::LADD"; case XCoreISD::LSUB : return "XCoreISD::LSUB"; + case XCoreISD::LMUL : return "XCoreISD::LMUL"; case XCoreISD::MACCU : return "XCoreISD::MACCU"; case XCoreISD::MACCS : return "XCoreISD::MACCS"; case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; @@ -573,9 +574,9 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); SDValue Zero = DAG.getConstant(0, MVT::i32); - SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, - DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, - LHS, RHS); + SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, + DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, + Zero, Zero); SDValue Lo(Hi.getNode(), 1); SDValue Ops[] = { Lo, Hi }; return DAG.getMergeValues(Ops, 2, dl); diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index 6b467c3f9c..6928138386 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -54,6 +54,9 @@ namespace llvm { // Corresponds to LSUB instruction LSUB, + // Corresponds to LMUL instruction + LMUL, + // Corresponds to MACCU instruction MACCU, diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index c42c2f59cd..c06fe5a20b 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -8,10 +8,7 @@ entry: } ; CHECK: umul_lohi: ; CHECK: ldc r2, 0 -; CHECK-NEXT: mov r3, r2 -; CHECK-NEXT: maccu r2, r3, r1, r0 -; CHECK-NEXT: mov r0, r3 -; CHECK-NEXT: mov r1, r2 +; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2 ; CHECK-NEXT: retsp 0 define i64 @smul_lohi(i32 %a, i32 %b) { |