diff options
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 12 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 5 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 17 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 | ||||
| -rw-r--r-- | utils/TableGen/DAGISelEmitter.cpp | 21 |
5 files changed, 0 insertions, 58 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 6cea5d6d7a..7d748259cf 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -327,18 +327,6 @@ namespace ISD { /// elements 1 to N-1 of the N-element vector are undefined. SCALAR_TO_VECTOR, - // EXTRACT_SUBREG - This node is used to extract a sub-register value. - // This node takes a superreg and a constant sub-register index as operands. - // Note sub-register indices must be increasing. That is, if the - // sub-register index of a 8-bit sub-register is N, then the index for a - // 16-bit sub-register must be at least N+1. - EXTRACT_SUBREG, - - // INSERT_SUBREG - This node is used to insert a sub-register value. - // This node takes a superreg, a subreg value, and a constant sub-register - // index as operands. - INSERT_SUBREG, - // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing // an unsigned/signed value of type i[2*N], then return the top part. MULHU, MULHS, diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 5d1b37d1c7..7f39bb2f83 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -406,11 +406,6 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; -def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG", - SDTypeProfile<1, 2, []>>; -def insert_subreg : SDNode<"ISD::INSERT_SUBREG", - SDTypeProfile<1, 3, []>>; - // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use // these internally. Don't reference these directly. def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 8d1ea8d3a4..a2c5396bb9 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1589,23 +1589,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { AddLegalizedOperand(SDValue(Node, i), Tmp1); } return Tmp2; - case ISD::EXTRACT_SUBREG: { - Tmp1 = LegalizeOp(Node->getOperand(0)); - ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); - assert(idx && "Operand must be a constant"); - Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); - } - break; - case ISD::INSERT_SUBREG: { - Tmp1 = LegalizeOp(Node->getOperand(0)); - Tmp2 = LegalizeOp(Node->getOperand(1)); - ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); - assert(idx && "Operand must be a constant"); - Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); - } - break; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { default: assert(0 && "This action is not supported yet!"); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 448d760868..3ff0352f66 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5165,9 +5165,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SRA_PARTS: return "sra_parts"; case ISD::SRL_PARTS: return "srl_parts"; - case ISD::EXTRACT_SUBREG: return "extract_subreg"; - case ISD::INSERT_SUBREG: return "insert_subreg"; - // Conversion operators. case ISD::SIGN_EXTEND: return "sign_extend"; case ISD::ZERO_EXTEND: return "zero_extend"; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 447e0517d9..63912a1e4e 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1967,25 +1967,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) { << " MVT::Other, Tmp1, Tmp2, Chain);\n" << "}\n\n"; - OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n" - << " SDValue N0 = N.getOperand(0);\n" - << " SDValue N1 = N.getOperand(1);\n" - << " unsigned C = cast<ConstantSDNode>(N1)->getZExtValue();\n" - << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n" - << " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EXTRACT_SUBREG,\n" - << " N.getValueType(), N0, Tmp);\n" - << "}\n\n"; - - OS << "SDNode *Select_INSERT_SUBREG(const SDValue &N) {\n" - << " SDValue N0 = N.getOperand(0);\n" - << " SDValue N1 = N.getOperand(1);\n" - << " SDValue N2 = N.getOperand(2);\n" - << " unsigned C = cast<ConstantSDNode>(N2)->getZExtValue();\n" - << " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n" - << " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::INSERT_SUBREG,\n" - << " N.getValueType(), N0, N1, Tmp);\n" - << "}\n\n"; - OS << "// The main instruction selector code.\n" << "SDNode *SelectCode(SDValue N) {\n" << " MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT();\n" @@ -2020,8 +2001,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) { << " case ISD::DBG_LABEL: return Select_DBG_LABEL(N);\n" << " case ISD::EH_LABEL: return Select_EH_LABEL(N);\n" << " case ISD::DECLARE: return Select_DECLARE(N);\n" - << " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n" - << " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n" << " case ISD::UNDEF: return Select_UNDEF(N);\n"; // Loop over all of the case statements, emiting a call to each method we |