diff options
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 9 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 |
2 files changed, 13 insertions, 7 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index e1643e23d3..303c415d2e 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -178,10 +178,13 @@ public: /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. /// - /// This method returns the number and type of the resultant breakdown. + /// This method returns the number of registers needed, and the VT for each + /// register. It also returns the VT of the PackedType elements before they + /// are promoted/expanded. /// - MVT::ValueType getPackedTypeBreakdown(const PackedType *PTy, - unsigned &NE) const; + unsigned getPackedTypeBreakdown(const PackedType *PTy, + MVT::ValueType &PTyElementVT, + MVT::ValueType &PTyLegalElementVT) const; typedef std::vector<double>::const_iterator legal_fpimm_iterator; legal_fpimm_iterator legal_fpimm_begin() const { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index b9c10ce103..922245f553 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -148,11 +148,13 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { /// /// This method returns the number and type of the resultant breakdown. /// -MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, - unsigned &NumVals) const { +unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, + MVT::ValueType &PTyElementVT, + MVT::ValueType &PTyLegalElementVT) const { // Figure out the right, legal destination reg to copy into. unsigned NumElts = PTy->getNumElements(); MVT::ValueType EltTy = getValueType(PTy->getElementType()); + PTyElementVT = EltTy; unsigned NumVectorRegs = 1; @@ -170,13 +172,14 @@ MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy, VT = getVectorType(EltTy, NumElts); MVT::ValueType DestVT = getTypeToTransformTo(VT); + PTyLegalElementVT = DestVT; if (DestVT < VT) { // Value is expanded, e.g. i64 -> i16. - NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT)); + return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT)); } else { // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. - NumVals = NumVectorRegs; + return NumVectorRegs; } return DestVT; |