diff options
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 16 | ||||
| -rw-r--r-- | test/CodeGen/ARM/arm-and-tst-peephole.ll | 3 |
2 files changed, 2 insertions, 17 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 315ddcbc7e..864c5f9dbb 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1352,20 +1352,6 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const { SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; - case ARM::TSTri: { - if (&*MI->getParent()->begin() == MI) - return false; - const MachineInstr *AND = llvm::prior(MI); - if (AND->getOpcode() != ARM::ANDri) - return false; - if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() && - MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) { - SrcReg = AND->getOperand(0).getReg(); - CmpValue = 0; - return true; - } - } - break; } return false; @@ -1415,8 +1401,6 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, switch (MI->getOpcode()) { default: break; case ARM::ADDri: - case ARM::ANDri: - case ARM::t2ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 8d42a794fe..77bc9eec1a 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -17,7 +17,8 @@ tailrecurse: ; preds = %sw.bb, %entry %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; CHECK: ands r12, r12, #3 +; CHECK: and lr, r12, #3 +; CHECK-NEXT: tst r12, #3 ; CHECK-NEXT: beq LBB0_4 ; T2: movs r5, #3 |