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-rw-r--r--lib/Target/ARM/ARMAsmPrinter.cpp19
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp32
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td18
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp18
4 files changed, 72 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index fdb79e8f5e..367b3da439 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -76,6 +76,7 @@ namespace {
}
void printAddrMode1(const MachineInstr *MI, int opNum);
+ void printAddrMode2(const MachineInstr *MI, int opNum);
void printAddrMode5(const MachineInstr *MI, int opNum);
void printMemRegImm(const MachineInstr *MI, int opNum,
@@ -215,6 +216,24 @@ void ARMAsmPrinter::printAddrMode1(const MachineInstr *MI, int opNum) {
}
}
+void ARMAsmPrinter::printAddrMode2(const MachineInstr *MI, int opNum) {
+ const MachineOperand &Arg = MI->getOperand(opNum);
+ const MachineOperand &Offset = MI->getOperand(opNum + 1);
+ assert(Offset.isImmediate());
+
+ if (Arg.isConstantPoolIndex()) {
+ assert(Offset.getImmedValue() == 0);
+ printOperand(MI, opNum);
+ } else {
+ assert(Arg.isRegister());
+ O << '[';
+ printOperand(MI, opNum);
+ O << ", ";
+ printOperand(MI, opNum + 1);
+ O << ']';
+ }
+}
+
void ARMAsmPrinter::printAddrMode5(const MachineInstr *MI, int opNum) {
const MachineOperand &Arg = MI->getOperand(opNum);
const MachineOperand &Offset = MI->getOperand(opNum + 1);
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 767cf2bacb..d4f30fc1ae 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -754,6 +754,7 @@ public:
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
SDOperand &ShiftType);
+ bool SelectAddrMode2(SDOperand N, SDOperand &Arg, SDOperand &Offset);
bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset);
// Include the pieces autogenerated from the target description.
@@ -820,7 +821,7 @@ bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
int alignment = 2;
SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
- SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr);
+ SDNode *n = CurDAG->getTargetNode(ARM::LDR, MVT::i32, Addr, Z);
Arg = SDOperand(n, 0);
} else
Arg = CurDAG->getTargetConstant(val, MVT::i32);
@@ -852,6 +853,35 @@ bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
return true;
}
+bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand N, SDOperand &Arg,
+ SDOperand &Offset) {
+ //TODO: complete and cleanup!
+ SDOperand Zero = CurDAG->getTargetConstant(0, MVT::i32);
+ if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
+ Arg = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Offset = Zero;
+ return true;
+ }
+ if (N.getOpcode() == ISD::ADD) {
+ short imm = 0;
+ if (isInt12Immediate(N.getOperand(1), imm)) {
+ Offset = CurDAG->getTargetConstant(imm, MVT::i32);
+ if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
+ Arg = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
+ } else {
+ Arg = N.getOperand(0);
+ }
+ return true; // [r+i]
+ }
+ }
+ Offset = Zero;
+ if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
+ Arg = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
+ else
+ Arg = N;
+ return true;
+}
+
bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg,
SDOperand &Offset) {
//TODO: detect offset
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 281966b773..6945540da0 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -18,6 +18,11 @@ def op_addr_mode1 : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
}
+def op_addr_mode2 : Operand<iPTR> {
+ let PrintMethod = "printAddrMode2";
+ let MIOperandInfo = (ops ptr_rc, i32imm);
+}
+
def op_addr_mode5 : Operand<iPTR> {
let PrintMethod = "printAddrMode5";
let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -33,6 +38,9 @@ def memri : Operand<iPTR> {
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
[]>;
+//Addressing Mode 2: Load and Store Word or Unsigned Byte
+def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
+
//Addressing Mode 5: VFP load/store
def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
@@ -157,9 +165,9 @@ let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
}
-def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
+def LDR : InstARM<(ops IntRegs:$dst, op_addr_mode2:$addr),
"ldr $dst, $addr",
- [(set IntRegs:$dst, (load iaddr:$addr))]>;
+ [(set IntRegs:$dst, (load addr_mode2:$addr))]>;
def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldrb $dst, [$addr]",
@@ -177,9 +185,9 @@ def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldrsh $dst, [$addr]",
[(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
-def str : InstARM<(ops IntRegs:$src, memri:$addr),
- "str $src, $addr",
- [(store IntRegs:$src, iaddr:$addr)]>;
+def STR : InstARM<(ops IntRegs:$src, op_addr_mode2:$addr),
+ "str $src, $addr",
+ [(store IntRegs:$src, addr_mode2:$addr)]>;
def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"strb $src, [$addr]",
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 817c9faf45..4a8fa1ee4d 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -44,7 +44,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
+ BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::
@@ -52,7 +52,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
+ BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -128,12 +128,12 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
- assert (MI.getOpcode() == ARM::ldr ||
- MI.getOpcode() == ARM::str ||
+ assert (MI.getOpcode() == ARM::LDR ||
+ MI.getOpcode() == ARM::STR ||
MI.getOpcode() == ARM::lea_addri);
- unsigned FrameIdx = 2;
- unsigned OffIdx = 1;
+ unsigned FrameIdx = MI.getOpcode() == ARM::lea_addri ? 2 : 1;
+ unsigned OffIdx = MI.getOpcode() == ARM::lea_addri ? 1 : 2;
int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
@@ -195,8 +195,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addImm(0).addImm(ARMShift::LSL);
if (HasFP) {
- BuildMI(MBB, MBBI, ARM::str, 3)
- .addReg(ARM::R11).addImm(0).addReg(ARM::R13);
+ BuildMI(MBB, MBBI, ARM::STR, 3)
+ .addReg(ARM::R11).addReg(ARM::R13).addImm(0);
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
addImm(ARMShift::LSL);
}
@@ -214,7 +214,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
if (hasFP(MF)) {
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
addImm(ARMShift::LSL);
- BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R11).addImm(0).addReg(ARM::R13);
+ BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
}
//add sp, sp, #NumBytes
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-06-26 09:02:26 +0000