diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 13 |
2 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 0a988138a9..7c7257900f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -278,7 +278,6 @@ def brtarget : Operand<OtherVT>; // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand<i32> { - int NumOperands = 2; string EncoderMethod = "getRegisterListOpValue"; let PrintMethod = "printRegisterList"; } diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index fe6bd34a2b..296a5c9ce3 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -378,11 +378,14 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &) const { - // {12-8} = Rd - // {7-0} = count - unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8; - Binary |= MI.getOperand(Op + 1).getImm() & 0xFF; + SmallVectorImpl<MCFixup> &Fixups) const { + // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each + // register in the list, set the corresponding bit. + unsigned Binary = 0; + for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) { + unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg()); + Binary |= 1 << regno; + } return Binary; } |