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-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.td6
-rw-r--r--lib/Target/SparcV8/SparcV8RegisterInfo.td6
2 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index ca0bcdc171..d8d130ccf5 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -69,10 +69,10 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
+ G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index ca0bcdc171..d8d130ccf5 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -69,10 +69,10 @@ let Namespace = "V8" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
- O0, O1, O2, O3, O4, O5, O7,
- L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5,
+ G1, G2, G3, G4, G5, G6, G7,
+ O0, O1, O2, O3, O4, O5, O7,
// Non-allocatable regs
O6, I6, I7, G0]> {
let Methods = [{