diff options
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 20 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-128.ll | 34 |
2 files changed, 53 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 97ae6ec83c..fe11d77680 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -512,6 +512,26 @@ defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD, defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD, VEX_4V, VEX_W; +let Predicates = [HasAVX] in { + def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), + (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>; + def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), + (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>; + + def : Pat<(f32 (sint_to_fp GR32:$src)), + (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f32 (sint_to_fp GR64:$src)), + (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>; + def : Pat<(f64 (sint_to_fp GR32:$src)), + (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>; + def : Pat<(f64 (sint_to_fp GR64:$src)), + (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>; +} + defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32, "cvttss2si\t{$src, $dst|$dst, $src}">, XS; defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32, diff --git a/test/CodeGen/X86/avx-128.ll b/test/CodeGen/X86/avx-128.ll index c29cb5d36c..57a3826130 100644 --- a/test/CodeGen/X86/avx-128.ll +++ b/test/CodeGen/X86/avx-128.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s @z = common global <4 x float> zeroinitializer, align 16 @@ -20,3 +20,35 @@ entry: store double %conv, double* %d, align 8 ret void } + +; CHECK: vcvtsi2sdq (% +define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2sd (% +define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2ss (% +define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to float + ret float %conv +} + +; CHECK: vcvtsi2ssq (% +define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to float + ret float %conv +} |