diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 10 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 8 |
2 files changed, 5 insertions, 13 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index f38ddc2d92..49b0223643 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -36,14 +36,6 @@ def imm32_63 : ImmLeaf<i64, //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// - -// Logical -let isCommutable = 1 in -class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>: - FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c), - !strconcat(instr_asm, "\t$dst, $b, $c"), - [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>; - // Shifts class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm, SDNode OpNode, PatFrag PF>: @@ -118,7 +110,7 @@ def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>; def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>; def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>; -def NOR64 : LogicNOR64<0x00, 0x27, "nor">; +def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b9dcd1da1d..06b7de7e8e 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -292,10 +292,10 @@ class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : } // Logical -class LogicNOR<bits<6> op, bits<6> func, string instr_asm>: - FR<op, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt), +class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: + FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), !strconcat(instr_asm, "\t$rd, $rs, $rt"), - [(set CPURegs:$rd, (not (or CPURegs:$rs, CPURegs:$rt)))], IIAlu> { + [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { let shamt = 0; let isCommutable = 1; } @@ -649,7 +649,7 @@ def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; -def NOR : LogicNOR<0x00, 0x27, "nor">; +def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; /// Shift Instructions def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>; |