diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCCTRLoops.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 9 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/asym-regclass-copy.ll | 3 |
4 files changed, 3 insertions, 20 deletions
diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp index 5b20f81a3e..81a54d7015 100644 --- a/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -685,7 +685,7 @@ bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) { const TargetRegisterClass *SrcRC = MF->getRegInfo().getRegClass(TripCount->getReg()); CountReg = MF->getRegInfo().createVirtualRegister(RC); - unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ? + unsigned CopyOp = (isPPC64 && GPRC->hasSubClassEq(SrcRC)) ? (unsigned) PPC::EXTSW_32_64 : (unsigned) TargetOpcode::COPY; BuildMI(*Preheader, InsertPos, dl, diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 975a7174f6..d2b1d6d392 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -366,15 +366,6 @@ def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), "xor $rA, $rS, $rB", IntSimple, [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; -// Moves between 32-bit and 64-bit registers (used for copy resolution -// after register allocation). -let isCodeGenOnly = 1 in { -def OR8_32 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), - "or $rA, $rS, $rB", IntSimple, []>; -def OR_64 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), - "or $rA, $rS, $rB", IntSimple, []>; -} - // Logical ops with immediate. def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), "andi. $dst, $src1, $src2", IntGeneral, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 2b71f67331..cf39386c67 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -422,15 +422,6 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opc = PPC::VOR; else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) Opc = PPC::CROR; - - // Asymmetric copies: - - else if (PPC::GPRCRegClass.contains(DestReg) && - PPC::G8RCRegClass.contains(SrcReg)) - Opc = PPC::OR_64; - else if (PPC::G8RCRegClass.contains(DestReg) && - PPC::GPRCRegClass.contains(SrcReg)) - Opc = PPC::OR8_32; else llvm_unreachable("Impossible reg-to-reg copy"); diff --git a/test/CodeGen/PowerPC/asym-regclass-copy.ll b/test/CodeGen/PowerPC/asym-regclass-copy.ll index c399802a1e..d04a6c98ee 100644 --- a/test/CodeGen/PowerPC/asym-regclass-copy.ll +++ b/test/CodeGen/PowerPC/asym-regclass-copy.ll @@ -2,7 +2,8 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; This test triggers the use of the asymmetric OR8_32 copy pattern. +; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with +; GPRC is handled correctly. When it was not, this test would assert. @gen_random.last = external unnamed_addr global i64, align 8 @.str = external unnamed_addr constant [4 x i8], align 1 |