diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 40 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 | ||||
| -rw-r--r-- | test/MC/ARM/arm_addrmode2.s | 1 |
3 files changed, 30 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index a400b7dfb0..e448164144 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2459,28 +2459,44 @@ def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, ldst_so_reg:$addr), - IndexModePost, StFrm, IIC_iStore_ru, - "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +let mayStore = 1, neverHasSideEffects = 1 in { +def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> addr; let Inst{25} = 1; + let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite + let Inst{19-16} = addr; + let Inst{11-5} = offset{11-5}; let Inst{4} = 0; - let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; + let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } -def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb), - (ins GPR:$Rt, addrmode_imm12:$addr), - IndexModePost, StFrm, IIC_iStore_ru, - "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb", - [/* For disassembly only; pattern left blank */]> { +def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), + (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), + IndexModePost, StFrm, IIC_iStore_ru, + "strt", "\t$Rt, $addr, $offset", + "$addr.base = $Rn_wb", []> { + // {12} isAdd + // {11-0} imm12/Rm + bits<14> offset; + bits<4> addr; let Inst{25} = 0; + let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite - let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; + let Inst{19-16} = addr; + let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } +} + multiclass AI3strT<bits<4> op, string opc> { def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 240293a2e6..201ccf8892 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -945,8 +945,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STR_POST_REG: case ARM::STRB_POST_IMM: case ARM::STRB_POST_REG: - case ARM::STRTr: - case ARM::STRTi: + case ARM::STRT_POST_REG: + case ARM::STRT_POST_IMM: case ARM::STRBT_POST_REG: case ARM::STRBT_POST_IMM: if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s index 76fe0275f2..ca99233b9b 100644 --- a/test/MC/ARM/arm_addrmode2.s +++ b/test/MC/ARM/arm_addrmode2.s @@ -1,5 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s -@ XFAIL: * @ Post-indexed @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] |