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-rw-r--r--CMakeLists.txt1
-rw-r--r--autoconf/configure.ac8
-rwxr-xr-xcmake/config-ix.cmake2
-rwxr-xr-xconfigure9
-rw-r--r--docs/CMake.html2
-rw-r--r--docs/CodeGenerator.html8
-rw-r--r--docs/CompilerWriterInfo.html12
-rw-r--r--docs/UsingLibraries.html10
-rw-r--r--include/llvm/ADT/Triple.h1
-rw-r--r--include/llvm/Intrinsics.td1
-rw-r--r--include/llvm/IntrinsicsAlpha.td18
-rw-r--r--lib/Support/Triple.cpp7
-rw-r--r--lib/Target/Alpha/Alpha.h43
-rw-r--r--lib/Target/Alpha/Alpha.td68
-rw-r--r--lib/Target/Alpha/AlphaAsmPrinter.cpp166
-rw-r--r--lib/Target/Alpha/AlphaBranchSelector.cpp66
-rw-r--r--lib/Target/Alpha/AlphaCallingConv.td38
-rw-r--r--lib/Target/Alpha/AlphaFrameLowering.cpp143
-rw-r--r--lib/Target/Alpha/AlphaFrameLowering.h43
-rw-r--r--lib/Target/Alpha/AlphaISelDAGToDAG.cpp425
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp962
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.h142
-rw-r--r--lib/Target/Alpha/AlphaInstrFormats.td268
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.cpp382
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.h85
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.td1159
-rw-r--r--lib/Target/Alpha/AlphaLLRP.cpp158
-rw-r--r--lib/Target/Alpha/AlphaMachineFunctionInfo.h62
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp199
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.h56
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.td133
-rw-r--r--lib/Target/Alpha/AlphaRelocations.h31
-rw-r--r--lib/Target/Alpha/AlphaSchedule.td85
-rw-r--r--lib/Target/Alpha/AlphaSelectionDAGInfo.cpp23
-rw-r--r--lib/Target/Alpha/AlphaSelectionDAGInfo.h31
-rw-r--r--lib/Target/Alpha/AlphaSubtarget.cpp35
-rw-r--r--lib/Target/Alpha/AlphaSubtarget.h49
-rw-r--r--lib/Target/Alpha/AlphaTargetMachine.cpp51
-rw-r--r--lib/Target/Alpha/AlphaTargetMachine.h66
-rw-r--r--lib/Target/Alpha/CMakeLists.txt38
-rw-r--r--lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.cpp23
-rw-r--r--lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.h29
-rw-r--r--lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp78
-rw-r--r--lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h40
-rw-r--r--lib/Target/Alpha/MCTargetDesc/CMakeLists.txt11
-rw-r--r--lib/Target/Alpha/MCTargetDesc/Makefile16
-rw-r--r--lib/Target/Alpha/Makefile21
-rw-r--r--lib/Target/Alpha/README.txt42
-rw-r--r--lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp20
-rw-r--r--lib/Target/Alpha/TargetInfo/CMakeLists.txt13
-rw-r--r--lib/Target/Alpha/TargetInfo/Makefile15
-rw-r--r--projects/sample/autoconf/configure.ac8
-rwxr-xr-xprojects/sample/configure9
-rw-r--r--test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll40
-rw-r--r--test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll27
-rw-r--r--test/CodeGen/Alpha/2006-01-26-VaargBreak.ll14
-rw-r--r--test/CodeGen/Alpha/2006-04-04-zextload.ll30
-rw-r--r--test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll18
-rw-r--r--test/CodeGen/Alpha/2006-11-01-vastart.ll15
-rw-r--r--test/CodeGen/Alpha/2007-11-27-mulneg3.ll13
-rw-r--r--test/CodeGen/Alpha/2008-11-10-smul_lohi.ll22
-rw-r--r--test/CodeGen/Alpha/2008-11-12-Add128.ll14
-rw-r--r--test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll6
-rw-r--r--test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll28
-rw-r--r--test/CodeGen/Alpha/2010-08-01-mulreduce64.ll11
-rw-r--r--test/CodeGen/Alpha/add.ll178
-rw-r--r--test/CodeGen/Alpha/add128.ll9
-rw-r--r--test/CodeGen/Alpha/bic.ll9
-rw-r--r--test/CodeGen/Alpha/bsr.ll12
-rw-r--r--test/CodeGen/Alpha/call_adj.ll13
-rw-r--r--test/CodeGen/Alpha/cmov.ll23
-rw-r--r--test/CodeGen/Alpha/cmpbge.ll16
-rw-r--r--test/CodeGen/Alpha/ctlz.ll14
-rw-r--r--test/CodeGen/Alpha/ctlz_e.ll11
-rw-r--r--test/CodeGen/Alpha/ctpop.ll17
-rw-r--r--test/CodeGen/Alpha/dg.exp5
-rw-r--r--test/CodeGen/Alpha/eqv.ll10
-rw-r--r--test/CodeGen/Alpha/i32_sub_1.ll9
-rw-r--r--test/CodeGen/Alpha/illegal-element-type.ll23
-rw-r--r--test/CodeGen/Alpha/jmp_table.ll99
-rw-r--r--test/CodeGen/Alpha/mb.ll6
-rw-r--r--test/CodeGen/Alpha/mul128.ll7
-rw-r--r--test/CodeGen/Alpha/mul5.ll33
-rw-r--r--test/CodeGen/Alpha/neg1.ll7
-rw-r--r--test/CodeGen/Alpha/not.ll8
-rw-r--r--test/CodeGen/Alpha/ornot.ll10
-rw-r--r--test/CodeGen/Alpha/private.ll19
-rw-r--r--test/CodeGen/Alpha/rpcc.ll9
-rw-r--r--test/CodeGen/Alpha/srl_and.ll10
-rw-r--r--test/CodeGen/Alpha/sub128.ll9
-rw-r--r--test/CodeGen/Alpha/weak.ll16
-rw-r--r--test/CodeGen/Alpha/zapnot.ll9
-rw-r--r--test/CodeGen/Alpha/zapnot2.ll9
-rw-r--r--test/CodeGen/Alpha/zapnot3.ll15
-rw-r--r--test/CodeGen/Alpha/zapnot4.ll7
-rw-r--r--tools/bugpoint/ToolRunner.cpp3
-rw-r--r--utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp2
-rw-r--r--utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp2
98 files changed, 12 insertions, 6266 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt
index f3ff1979c9..139169db3d 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -64,7 +64,6 @@ Please clean the source directory.")
endif()
set(LLVM_ALL_TARGETS
- Alpha
ARM
CBackend
CellSPU
diff --git a/autoconf/configure.ac b/autoconf/configure.ac
index 89f846749c..8b64ce11d5 100644
--- a/autoconf/configure.ac
+++ b/autoconf/configure.ac
@@ -352,7 +352,6 @@ AC_CACHE_CHECK([target architecture],[llvm_cv_target_arch],
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -487,7 +486,6 @@ else
Sparc) AC_SUBST(TARGET_HAS_JIT,0) ;;
PowerPC) AC_SUBST(TARGET_HAS_JIT,1) ;;
x86_64) AC_SUBST(TARGET_HAS_JIT,1) ;;
- Alpha) AC_SUBST(TARGET_HAS_JIT,0) ;;
ARM) AC_SUBST(TARGET_HAS_JIT,1) ;;
Mips) AC_SUBST(TARGET_HAS_JIT,1) ;;
XCore) AC_SUBST(TARGET_HAS_JIT,0) ;;
@@ -603,21 +601,20 @@ dnl Allow specific targets to be specified for building (or not)
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
- host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ host, x86, x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -632,7 +629,6 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
diff --git a/cmake/config-ix.cmake b/cmake/config-ix.cmake
index 0381dbf496..18549a3b22 100755
--- a/cmake/config-ix.cmake
+++ b/cmake/config-ix.cmake
@@ -309,8 +309,6 @@ elseif (LLVM_NATIVE_ARCH MATCHES "sparc")
set(LLVM_NATIVE_ARCH Sparc)
elseif (LLVM_NATIVE_ARCH MATCHES "powerpc")
set(LLVM_NATIVE_ARCH PowerPC)
-elseif (LLVM_NATIVE_ARCH MATCHES "alpha")
- set(LLVM_NATIVE_ARCH Alpha)
elseif (LLVM_NATIVE_ARCH MATCHES "arm")
set(LLVM_NATIVE_ARCH ARM)
elseif (LLVM_NATIVE_ARCH MATCHES "mips")
diff --git a/configure b/configure
index a82cccb3f9..a1eb3b1d5d 100755
--- a/configure
+++ b/configure
@@ -1415,7 +1415,7 @@ Optional Features:
(default is YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, alpha, arm, mips, spu,
+ x86_64, sparc, powerpc, arm, mips, spu,
xcore, msp430, ptx, cbe, and cpp (default=all)
--enable-cbe-printf-a Enable C Backend output with hex floating point via
%a (default is YES)
@@ -3874,7 +3874,6 @@ else
amd64-* | x86_64-*) llvm_cv_target_arch="x86_64" ;;
sparc*-*) llvm_cv_target_arch="Sparc" ;;
powerpc*-*) llvm_cv_target_arch="PowerPC" ;;
- alpha*-*) llvm_cv_target_arch="Alpha" ;;
arm*-*) llvm_cv_target_arch="ARM" ;;
mips-*) llvm_cv_target_arch="Mips" ;;
xcore-*) llvm_cv_target_arch="XCore" ;;
@@ -5072,8 +5071,6 @@ else
;;
x86_64) TARGET_HAS_JIT=1
;;
- Alpha) TARGET_HAS_JIT=0
- ;;
ARM) TARGET_HAS_JIT=1
;;
Mips) TARGET_HAS_JIT=1
@@ -5270,14 +5267,13 @@ if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CBackend CppBackend MBlaze PTX" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
@@ -5292,7 +5288,6 @@ case "$enableval" in
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;;
PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;;
- Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;;
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
diff --git a/docs/CMake.html b/docs/CMake.html
index ac07b0d6d4..90ead41df5 100644
--- a/docs/CMake.html
+++ b/docs/CMake.html
@@ -249,7 +249,7 @@
<dd>Semicolon-separated list of targets to build, or <i>all</i> for
building all targets. Case-sensitive. For Visual C++ defaults
to <i>X86</i>. On the other cases defaults to <i>all</i>. Example:
- <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC;Alpha"</i>.</dd>
+ <i>-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</i>.</dd>
<dt><b>LLVM_BUILD_TOOLS</b>:BOOL</dt>
<dd>Build LLVM tools. Defaults to ON. Targets for building each tool
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 8bb680c487..15344da16d 100644
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -2208,7 +2208,6 @@ is the key:</p>
<tr>
<th>Feature</th>
<th>ARM</th>
- <th>Alpha</th>
<th>CellSPU</th>
<th>MBlaze</th>
<th>MSP430</th>
@@ -2223,7 +2222,6 @@ is the key:</p>
<tr>
<td><a href="#feat_reliable">is generally reliable</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2238,7 +2236,6 @@ is the key:</p>
<tr>
<td><a href="#feat_asmparser">assembly parser</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2253,7 +2250,6 @@ is the key:</p>
<tr>
<td><a href="#feat_disassembler">disassembler</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2268,7 +2264,6 @@ is the key:</p>
<tr>
<td><a href="#feat_inlineasm">inline asm</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2283,7 +2278,6 @@ is the key:</p>
<tr>
<td><a href="#feat_jit">jit</a></td>
<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
@@ -2298,7 +2292,6 @@ is the key:</p>
<tr>
<td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
<td class="no"></td> <!-- ARM -->
- <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
@@ -2313,7 +2306,6 @@ is the key:</p>
<tr>
<td><a href="#feat_tailcall">tail calls</a></td>
<td class="yes"></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
diff --git a/docs/CompilerWriterInfo.html b/docs/CompilerWriterInfo.html
index d9201fc8a4..857a1d413a 100644
--- a/docs/CompilerWriterInfo.html
+++ b/docs/CompilerWriterInfo.html
@@ -21,7 +21,6 @@
<ol>
<li><a href="#hw">Hardware</a>
<ol>