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-rw-r--r--include/llvm/Target/Target.td2
-rw-r--r--lib/CodeGen/MachineInstr.cpp4
-rw-r--r--lib/CodeGen/PeepholeOptimizer.cpp4
-rw-r--r--lib/CodeGen/VirtRegRewriter.cpp3
4 files changed, 9 insertions, 4 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index f7a029bd61..e88a09eecc 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -484,7 +484,7 @@ def DBG_VALUE : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "DBG_VALUE";
- let isAsCheapAsAMove = 1;
+ let neverHasSideEffects = 1;
}
def REG_SEQUENCE : Instruction {
let OutOperandList = (outs unknown:$dst);
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index bc2a545a5f..ccb2ffbab1 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -1115,7 +1115,9 @@ bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
SawStore = true;
return false;
}
- if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
+
+ if (isLabel() || isDebugValue() ||
+ TID->isTerminator() || TID->hasUnmodeledSideEffects())
return false;
// See if this instruction does a load. If so, we have to guarantee that the
diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp
index 07c2b80dcb..1ddfe8b7c2 100644
--- a/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/lib/CodeGen/PeepholeOptimizer.cpp
@@ -336,7 +336,9 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
MachineInstr *MI = &*MII++;
LocalMIs.insert(MI);
- if (MI->getDesc().hasUnmodeledSideEffects())
+ if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
+ MI->isKill() || MI->isInlineAsm() || MI->isDebugValue() ||
+ MI->getDesc().hasUnmodeledSideEffects())
continue;
if (MI->getDesc().isCompare()) {
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 14ee69da4c..d04b9285ba 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -1620,7 +1620,8 @@ static bool isSafeToDelete(MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
TID.isCall() || TID.isBarrier() || TID.isReturn() ||
- TID.hasUnmodeledSideEffects())
+ TID.hasUnmodeledSideEffects() ||
+ MI.isLabel() || MI.isDebugValue())
return false;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);