diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64InstrInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 2 |
5 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 2b0450b971..37156c4c10 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -52,7 +52,7 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, return true; case ARM::MOVr: case ARM::tMOVr: - assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && + assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "Invalid ARM MOV instruction"); SrcReg = MI.getOperand(1).getReg(); diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 71bf5b0e96..04b08b58bf 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -33,7 +33,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, oc == Alpha::CPYSTs) { // or r1, r2, r2 // cpys(s|t) r1 r2 r2 - assert(MI.getNumOperands() == 3 && + assert(MI.getNumOperands() >= 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && MI.getOperand(2).isRegister() && diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 624d53a123..aabdee37cb 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -30,7 +30,7 @@ bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI, MachineOpCode oc = MI.getOpcode(); if (oc == IA64::MOV || oc == IA64::FMOV) { // TODO: this doesn't detect predicate moves - assert(MI.getNumOperands() == 2 && + assert(MI.getNumOperands() >= 2 && /* MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && */ "invalid register-register move instruction"); diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 1ba701f6a7..89b5c9c890 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -38,7 +38,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, MachineOpCode oc = MI.getOpcode(); if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 - assert(MI.getNumOperands() == 3 && + assert(MI.getNumOperands() >= 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && MI.getOperand(2).isRegister() && @@ -49,7 +49,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, return true; } } else if (oc == PPC::ADDI) { // addi r1, r2, 0 - assert(MI.getNumOperands() == 3 && + assert(MI.getNumOperands() >= 3 && MI.getOperand(0).isRegister() && MI.getOperand(2).isImmediate() && "invalid PPC ADDI instruction!"); @@ -59,7 +59,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, return true; } } else if (oc == PPC::ORI) { // ori r1, r2, 0 - assert(MI.getNumOperands() == 3 && + assert(MI.getNumOperands() >= 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && MI.getOperand(2).isImmediate() && @@ -71,7 +71,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, } } else if (oc == PPC::FMRS || oc == PPC::FMRD || oc == PPC::FMRSD) { // fmr r1, r2 - assert(MI.getNumOperands() == 2 && + assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "invalid PPC FMR instruction"); @@ -79,7 +79,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, destReg = MI.getOperand(0).getReg(); return true; } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 - assert(MI.getNumOperands() == 2 && + assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "invalid PPC MCRF instruction"); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 7a3dfe06da..bd46cda376 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -39,7 +39,7 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { - assert(MI.getNumOperands() == 2 && + assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "invalid register-register move instruction"); |