diff options
| -rw-r--r-- | lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp | 17 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.cpp | 42 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 17 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/01-RetArg.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/01-RetImm.ll | 6 |
5 files changed, 80 insertions, 8 deletions
diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp index 1c1e2554b7..7e3b79a7da 100644 --- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp @@ -168,5 +168,20 @@ void SystemZAsmPrinter::printMachineInstruction(const MachineInstr *MI) { void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, const char* Modifier) { - assert(0 && "Not implemented yet!"); + const MachineOperand &MO = MI->getOperand(OpNum); + switch (MO.getType()) { + case MachineOperand::MO_Register: + assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Virtual registers should be already mapped!"); + O << '%' << TM.getRegisterInfo()->get(MO.getReg()).AsmName; + return; + case MachineOperand::MO_Immediate: + O << MO.getImm(); + return; + case MachineOperand::MO_MachineBasicBlock: + printBasicBlockLabel(MO.getMBB()); + return; + default: + assert(0 && "Not implemented yet!"); + } } diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 5747126a4d..5137a1534c 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -43,18 +43,46 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + + if (DestRC == SrcRC) { + unsigned Opc; + if (DestRC == &SystemZ::GR64RegClass) { + Opc = SystemZ::MOV64rr; + } else { + return false; + } + + BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg); + return true; + } + return false; } bool SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - return false; + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const { + SrcSubIdx = DstSubIdx = 0; // No sub-registers yet. + + switch (MI.getOpcode()) { + default: + return false; + case SystemZ::MOV64rr: + assert(MI.getNumOperands() >= 2 && + MI.getOperand(0).isReg() && + MI.getOperand(1).isReg() && + "invalid register-register move instruction"); + SrcReg = MI.getOperand(1).getReg(); + DstReg = MI.getOperand(0).getReg(); + return true; + } } bool diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 54e0969bc5..9b961cbdab 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -30,3 +30,20 @@ def NOP : Pseudo<(outs), (ins), "# no-op", []>; let isReturn = 1, isTerminator = 1 in { def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>; } + +//===----------------------------------------------------------------------===// +// Move Instructions + +// FIXME: Provide proper encoding! +let neverHasSideEffects = 1 in { +def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src), + "lgr\t{$dst, $src}", + []>; +} + +// FIXME: Provide proper encoding! +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV64ri : Pseudo<(outs GR64:$dst), (ins i64imm:$src), + "lghi\t{$dst, $src}", + [(set GR64:$dst, imm:$src)]>; +} diff --git a/test/CodeGen/SystemZ/01-RetArg.ll b/test/CodeGen/SystemZ/01-RetArg.ll new file mode 100644 index 0000000000..9377cc17fd --- /dev/null +++ b/test/CodeGen/SystemZ/01-RetArg.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=systemz + +define i64 @foo(i64 %a, i64 %b) { +entry: + ret i64 %b +}
\ No newline at end of file diff --git a/test/CodeGen/SystemZ/01-RetImm.ll b/test/CodeGen/SystemZ/01-RetImm.ll new file mode 100644 index 0000000000..d575040b8c --- /dev/null +++ b/test/CodeGen/SystemZ/01-RetImm.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=systemz + +define i64 @foo() { +entry: + ret i64 0 +}
\ No newline at end of file |