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-rw-r--r--lib/Target/X86/X86InstrSSE.td164
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp30
2 files changed, 102 insertions, 92 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index b53cdab4ae..892c4ce475 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -534,20 +534,20 @@ def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
Requires<[HasSSE2]>;
// Match intrinsics which expect XMM operand(s).
-def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
- "cvtss2si {$src, $dst|$dst, $src}",
- [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
-def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
- "cvtss2si {$src, $dst|$dst, $src}",
- [(set GR32:$dst, (int_x86_sse_cvtss2si
- (loadv4f32 addr:$src)))]>;
-def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
- "cvtsd2si {$src, $dst|$dst, $src}",
- [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
-def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
- "cvtsd2si {$src, $dst|$dst, $src}",
- [(set GR32:$dst, (int_x86_sse2_cvtsd2si
- (loadv2f64 addr:$src)))]>;
+def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
+ "cvtss2si {$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
+def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
+ "cvtss2si {$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (int_x86_sse_cvtss2si
+ (loadv4f32 addr:$src)))]>;
+def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
+ "cvtsd2si {$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
+def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
+ "cvtsd2si {$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (int_x86_sse2_cvtsd2si
+ (loadv2f64 addr:$src)))]>;
// Aliases for intrinsics
def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
@@ -884,81 +884,81 @@ def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
SSE_splat_v2_mask)))]>;
// SSE2 instructions without OpSize prefix
-def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtdq2ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
- TB, Requires<[HasSSE2]>;
-def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
- "cvtdq2ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
- (bc_v4i32 (loadv2i64 addr:$src))))]>,
- TB, Requires<[HasSSE2]>;
+def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtdq2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
+ TB, Requires<[HasSSE2]>;
+def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
+ "cvtdq2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+ (bc_v4i32 (loadv2i64 addr:$src))))]>,
+ TB, Requires<[HasSSE2]>;
// SSE2 instructions with XS prefix
-def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtdq2pd {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
- XS, Requires<[HasSSE2]>;
-def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
- "cvtdq2pd {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
- (bc_v4i32 (loadv2i64 addr:$src))))]>,
- XS, Requires<[HasSSE2]>;
-
-def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtps2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
-def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "cvtps2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtps2dq
- (loadv4f32 addr:$src)))]>;
+def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtdq2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
+ XS, Requires<[HasSSE2]>;
+def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ "cvtdq2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
+ (bc_v4i32 (loadv2i64 addr:$src))))]>,
+ XS, Requires<[HasSSE2]>;
+
+def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtps2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
+def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ "cvtps2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtps2dq
+ (loadv4f32 addr:$src)))]>;
// SSE2 packed instructions with XS prefix
-def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvttps2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
- XS, Requires<[HasSSE2]>;
-def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "cvttps2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvttps2dq
- (loadv4f32 addr:$src)))]>,
- XS, Requires<[HasSSE2]>;
+def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvttps2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
+ XS, Requires<[HasSSE2]>;
+def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ "cvttps2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvttps2dq
+ (loadv4f32 addr:$src)))]>,
+ XS, Requires<[HasSSE2]>;
// SSE2 packed instructions with XD prefix
-def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtpd2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
- XD, Requires<[HasSSE2]>;
-def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "cvtpd2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
- (loadv2f64 addr:$src)))]>,
- XD, Requires<[HasSSE2]>;
-def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvttpd2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
-def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
- "cvttpd2dq {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
- (loadv2f64 addr:$src)))]>;
+def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtpd2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
+ XD, Requires<[HasSSE2]>;
+def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ "cvtpd2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
+ (loadv2f64 addr:$src)))]>,
+ XD, Requires<[HasSSE2]>;
+def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvttpd2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
+def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
+ "cvttpd2dq {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
+ (loadv2f64 addr:$src)))]>;
// SSE2 instructions without OpSize prefix
-def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtps2pd {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
- TB, Requires<[HasSSE2]>;
-def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
- "cvtps2pd {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtps2pd
- (loadv4f32 addr:$src)))]>,
- TB, Requires<[HasSSE2]>;
-
-def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
- "cvtpd2ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
-def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
- "cvtpd2ps {$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
- (loadv2f64 addr:$src)))]>;
+def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtps2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
+ TB, Requires<[HasSSE2]>;
+def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
+ "cvtps2pd {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtps2pd
+ (loadv4f32 addr:$src)))]>,
+ TB, Requires<[HasSSE2]>;
+
+def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
+ "cvtpd2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
+def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
+ "cvtpd2ps {$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
+ (loadv2f64 addr:$src)))]>;
// Match intrinsics which expect XMM operand(s).
// Aliases for intrinsics
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index a0c9b0c287..58180b61ff 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -434,9 +434,11 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
// Scalar SSE instructions
case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
- case X86::CVTSS2SIrr:return MakeRMInst(X86::CVTSS2SIrm, FrameIndex, MI);
+ case X86::Int_CVTSS2SIrr:
+ return MakeRMInst(X86::Int_CVTSS2SIrm, FrameIndex, MI);
case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI);
- case X86::CVTSD2SIrr:return MakeRMInst(X86::CVTSD2SIrm, FrameIndex, MI);
+ case X86::Int_CVTSD2SIrr:
+ return MakeRMInst(X86::Int_CVTSD2SIrm, FrameIndex, MI);
case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI);
case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI);
case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI);
@@ -480,14 +482,22 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
case X86::MOVSHDUPrr:return MakeRMInst(X86::MOVSHDUPrm, FrameIndex, MI);
case X86::MOVSLDUPrr:return MakeRMInst(X86::MOVSLDUPrm, FrameIndex, MI);
case X86::MOVDDUPrr: return MakeRMInst(X86::MOVDDUPrm, FrameIndex, MI);
- case X86::CVTDQ2PSrr:return MakeRMInst(X86::CVTDQ2PSrm, FrameIndex, MI);
- case X86::CVTDQ2PDrr:return MakeRMInst(X86::CVTDQ2PDrm, FrameIndex, MI);
- case X86::CVTPS2DQrr:return MakeRMInst(X86::CVTPS2DQrm, FrameIndex, MI);
- case X86::CVTTPS2DQrr:return MakeRMInst(X86::CVTTPS2DQrm, FrameIndex, MI);
- case X86::CVTPD2DQrr:return MakeRMInst(X86::CVTPD2DQrm, FrameIndex, MI);
- case X86::CVTTPD2DQrr:return MakeRMInst(X86::CVTTPD2DQrm, FrameIndex, MI);
- case X86::CVTPS2PDrr:return MakeRMInst(X86::CVTPS2PDrm, FrameIndex, MI);
- case X86::CVTPD2PSrr:return MakeRMInst(X86::CVTPD2PSrm, FrameIndex, MI);
+ case X86::Int_CVTDQ2PSrr:
+ return MakeRMInst(X86::Int_CVTDQ2PSrm, FrameIndex, MI);
+ case X86::Int_CVTDQ2PDrr:
+ return MakeRMInst(X86::Int_CVTDQ2PDrm, FrameIndex, MI);
+ case X86::Int_CVTPS2DQrr:
+ return MakeRMInst(X86::Int_CVTPS2DQrm, FrameIndex, MI);
+ case X86::Int_CVTTPS2DQrr:
+ return MakeRMInst(X86::Int_CVTTPS2DQrm, FrameIndex, MI);
+ case X86::Int_CVTPD2DQrr:
+ return MakeRMInst(X86::Int_CVTPD2DQrm, FrameIndex, MI);
+ case X86::Int_CVTTPD2DQrr:
+ return MakeRMInst(X86::Int_CVTTPD2DQrm, FrameIndex, MI);
+ case X86::Int_CVTPS2PDrr:
+ return MakeRMInst(X86::Int_CVTPS2PDrm, FrameIndex, MI);
+ case X86::Int_CVTPD2PSrr:
+ return MakeRMInst(X86::Int_CVTPD2PSrm, FrameIndex, MI);
case X86::Int_CVTSI2SDrr:
return MakeRMInst(X86::Int_CVTSI2SDrm, FrameIndex, MI);
case X86::Int_CVTSD2SSrr:
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-04 04:00:31 +0000